Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_ddrc_ctrl | 0x0 | 32 | DDRC Control | | |
ab_Two_rank_cfg | 0x4 | 32 | Two Rank Configuration | | |
ab_HPR_reg | 0x8 | 32 | HPR Queue control | | |
ab_LPR_reg | 0xc | 32 | LPR Queue control | | |
ab_WR_reg | 0x10 | 32 | WR Queue control | | |
ab_DRAM_param_reg0 | 0x14 | 32 | DRAM Parameters 0 | | |
ab_DRAM_param_reg1 | 0x18 | 32 | DRAM Parameters 1 | | |
ab_DRAM_param_reg2 | 0x1c | 32 | DRAM Parameters 2 | | |
ab_DRAM_param_reg3 | 0x20 | 32 | DRAM Parameters 3 | | |
ab_DRAM_param_reg4 | 0x24 | 32 | DRAM Parameters 4 | | |
ab_DRAM_init_param | 0x28 | 32 | DRAM Initialization Parameters | | |
ab_DRAM_EMR_reg | 0x2c | 32 | DRAM EMR2, EMR3 access | | |
ab_DRAM_EMR_MR_reg | 0x30 | 32 | DRAM EMR, MR access | | |
ab_DRAM_burst8_rdwr | 0x34 | 32 | DRAM Burst 8 read/write | | |
ab_DRAM_disable_DQ | 0x38 | 32 | DRAM Disable DQ | | |
ab_DRAM_addr_map_bank | 0x3c | 32 | Row/Column address bits | | |
ab_DRAM_addr_map_col | 0x40 | 32 | Column address bits | | |
ab_DRAM_addr_map_row | 0x44 | 32 | Select DRAM row address bits | | |
ab_DRAM_ODT_reg | 0x48 | 32 | DRAM ODT control | | |
ab_phy_dbg_reg | 0x4c | 32 | PHY debug | | |
ab_phy_cmd_timeout_rddata_cpt | 0x50 | 32 | PHY command time out and read data capture FIFO | | |
ab_mode_sts_reg | 0x54 | 32 | Controller operation mode status | | |
ab_DLL_calib | 0x58 | 32 | DLL calibration | | |
ab_ODT_delay_hold | 0x5c | 32 | ODT delay and ODT hold | | |
ab_ctrl_reg1 | 0x60 | 32 | Controller 1 | | |
ab_ctrl_reg2 | 0x64 | 32 | Controller 2 | | |
ab_ctrl_reg3 | 0x68 | 32 | Controller 3 | | |
ab_ctrl_reg4 | 0x6c | 32 | Controller 4 | | |
ab_ctrl_reg5 | 0x78 | 32 | Controller register 5 | | |
ab_ctrl_reg6 | 0x7c | 32 | Controller register 6 | | |
ab_CHE_REFRESH_TIMER01 | 0xa0 | 32 | CHE_REFRESH_TIMER01 | | |
ab_CHE_T_ZQ | 0xa4 | 32 | ZQ parameters | | |
ab_CHE_T_ZQ_Short_Interval_Reg | 0xa8 | 32 | Misc parameters | | |
ab_deep_pwrdwn_reg | 0xac | 32 | Deep powerdown (LPDDR2) | | |
ab_reg_2c | 0xb0 | 32 | Training control | | |
ab_reg_2d | 0xb4 | 32 | Misc Debug | | |
ab_dfi_timing | 0xb8 | 32 | DFI timing | | |
ab_CHE_ECC_CONTROL_REG_OFFSET | 0xc4 | 32 | ECC error clear | | |
ab_CHE_CORR_ECC_LOG_REG_OFFSET | 0xc8 | 32 | ECC error correction | | |
ab_CHE_CORR_ECC_ADDR_REG_OFFSET | 0xcc | 32 | ECC error correction address log | | |
ab_CHE_CORR_ECC_DATA_31_0_REG_OFFSET | 0xd0 | 32 | ECC error correction data log low | | |
ab_CHE_CORR_ECC_DATA_63_32_REG_OFFSET | 0xd4 | 32 | ECC error correction data log mid | | |
ab_CHE_CORR_ECC_DATA_71_64_REG_OFFSET | 0xd8 | 32 | ECC error correction data log high | | |
ab_CHE_UNCORR_ECC_LOG_REG_OFFSET | 0xdc | 32 | ECC unrecoverable error status | | |
ab_CHE_UNCORR_ECC_ADDR_REG_OFFSET | 0xe0 | 32 | ECC unrecoverable error address | | |
ab_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET | 0xe4 | 32 | ECC unrecoverable error data low | | |
ab_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET | 0xe8 | 32 | ECC unrecoverable error data middle | | |
ab_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET | 0xec | 32 | ECC unrecoverable error data high | | |
ab_CHE_ECC_STATS_REG_OFFSET | 0xf0 | 32 | ECC error count | | |
ab_ECC_scrub | 0xf4 | 32 | ECC mode/scrub | | |
ab_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET | 0xf8 | 32 | ECC data mask low | | |
ab_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET | 0xfc | 32 | ECC data mask high | | |
ab_phy_rcvr_enable | 0x114 | 32 | Phy receiver enable register | | |
ab_PHY_Config0 | 0x118 | 32 | PHY configuration register for data slice 0. | | |
ab_PHY_Config1 | 0x11c | 32 | PHY configuration register for data slice 1. | | |
ab_PHY_Config2 | 0x120 | 32 | PHY configuration register for data slice 2. | | |
ab_PHY_Config3 | 0x124 | 32 | PHY configuration register for data slice 3. | | |
ab_phy_init_ratio0 | 0x12c | 32 | PHY init ratio register for data slice 0. | | |
ab_phy_init_ratio1 | 0x130 | 32 | PHY init ratio register for data slice 1. | | |
ab_phy_init_ratio2 | 0x134 | 32 | PHY init ratio register for data slice 2. | | |
ab_phy_init_ratio3 | 0x138 | 32 | PHY init ratio register for data slice 3. | | |
ab_phy_rd_dqs_cfg0 | 0x140 | 32 | PHY read DQS configuration register for data slice 0. | | |
ab_phy_rd_dqs_cfg1 | 0x144 | 32 | PHY read DQS configuration register for data slice 1. | | |
ab_phy_rd_dqs_cfg2 | 0x148 | 32 | PHY read DQS configuration register for data slice 2. | | |
ab_phy_rd_dqs_cfg3 | 0x14c | 32 | PHY read DQS configuration register for data slice 3. | | |
ab_phy_wr_dqs_cfg0 | 0x154 | 32 | PHY write DQS configuration register for data slice 0. | | |
ab_phy_wr_dqs_cfg1 | 0x158 | 32 | PHY write DQS configuration register for data slice 1. | | |
ab_phy_wr_dqs_cfg2 | 0x15c | 32 | PHY write DQS configuration register for data slice 2. | | |
ab_phy_wr_dqs_cfg3 | 0x160 | 32 | PHY write DQS configuration register for data slice 3. | | |
ab_phy_we_cfg0 | 0x168 | 32 | PHY FIFO write enable configuration for data slice 0. | | |
ab_phy_we_cfg1 | 0x16c | 32 | PHY FIFO write enable configuration for data slice 1. | | |
ab_phy_we_cfg2 | 0x170 | 32 | PHY FIFO write enable configuration for data slice 2. | | |
ab_phy_we_cfg3 | 0x174 | 32 | PHY FIFO write enable configuration for data slice 3. | | |
ab_wr_data_slv0 | 0x17c | 32 | PHY write data slave ratio config for data slice 0. | | |
ab_wr_data_slv1 | 0x180 | 32 | PHY write data slave ratio config for data slice 1. | | |
ab_wr_data_slv2 | 0x184 | 32 | PHY write data slave ratio config for data slice 2. | | |
ab_wr_data_slv3 | 0x188 | 32 | PHY write data slave ratio config for data slice 3. | | |
ab_reg_64 | 0x190 | 32 | Training control 2 | | |
ab_reg_65 | 0x194 | 32 | Training control 3 | | |
ab_reg69_6a0 | 0x1a4 | 32 | Training results for data slice 0. | | |
ab_reg69_6a1 | 0x1a8 | 32 | Training results for data slice 1. | | |
ab_reg6c_6d2 | 0x1b0 | 32 | Training results for data slice 2. | | |
ab_reg6c_6d3 | 0x1b4 | 32 | Training results for data slice 3. | | |
ab_reg6e_710 | 0x1b8 | 32 | Training results (2) for data slice 0. | | |
ab_reg6e_711 | 0x1bc | 32 | Training results (2) for data slice 1. | | |
ab_reg6e_712 | 0x1c0 | 32 | Training results (2) for data slice 2. | | |
ab_reg6e_713 | 0x1c4 | 32 | Training results (2) for data slice 3. | | |
ab_phy_dll_sts0 | 0x1cc | 32 | Slave DLL results for data slice 0. | | |
ab_phy_dll_sts1 | 0x1d0 | 32 | Slave DLL results for data slice 1. | | |
ab_phy_dll_sts2 | 0x1d4 | 32 | Slave DLL results for data slice 2. | | |
ab_phy_dll_sts3 | 0x1d8 | 32 | Slave DLL results for data slice 3. | | |
ab_dll_lock_sts | 0x1e0 | 32 | DLL Lock Status, read | | |
ab_phy_ctrl_sts | 0x1e4 | 32 | PHY Control status, read | | |
ab_phy_ctrl_sts_reg2 | 0x1e8 | 32 | PHY Control status (2), read | | |
ab_axi_id | 0x200 | 32 | ID and revision information page_mask 0x00000204 32 rw 0x00000000 Page mask | | |
ab_axi_priority_wr_port0 | 0x208 | 32 | AXI Priority control for write port 0. | | |
ab_axi_priority_wr_port1 | 0x20c | 32 | AXI Priority control for write port 1. | | |
ab_axi_priority_wr_port2 | 0x210 | 32 | AXI Priority control for write port 2. | | |
ab_axi_priority_wr_port3 | 0x214 | 32 | AXI Priority control for write port 3. | | |
ab_axi_priority_rd_port0 | 0x218 | 32 | AXI Priority control for read port 0. | | |
ab_axi_priority_rd_port1 | 0x21c | 32 | AXI Priority control for read port 1. | | |
ab_axi_priority_rd_port2 | 0x220 | 32 | AXI Priority control for read port 2. | | |
ab_axi_priority_rd_port3 | 0x224 | 32 | AXI Priority control for read port 3. | | |
ab_excl_access_cfg0 | 0x294 | 32 | Exclusive access configuration for port 0. | | |
ab_excl_access_cfg1 | 0x298 | 32 | Exclusive access configuration for port 1. | | |
ab_excl_access_cfg2 | 0x29c | 32 | Exclusive access configuration for port 2. | | |
ab_excl_access_cfg3 | 0x2a0 | 32 | Exclusive access configuration for port 3. | | |
ab_mode_reg_read | 0x2a4 | 32 | Mode register read data | | |
ab_lpddr_ctrl0 | 0x2a8 | 32 | LPDDR2 Control 0 | | |
ab_lpddr_ctrl1 | 0x2ac | 32 | LPDDR2 Control 1 | | |
ab_lpddr_ctrl2 | 0x2b0 | 32 | LPDDR2 Control 2 | | |
ab_lpddr_ctrl3 | 0x2b4 | 32 | LPDDR2 Control 3 | | |