OVP Peripheral Model: XilinxZynq7000Devcfg
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Zynq 7000 Platform Device Configuration Registers (devcfg)
Licensing
Open Source Apache 2.0
Limitations
This is mainly a register only interface model. It provides behavior to access the power rails using the XADC interface. The power rail data is provided by values stored in memory which can be updated externally. It provides the ability to lock and un-lock registers.
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
Location
The zynq_7000-devcfg peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-devcfg / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
board | string | The XADC interface includes default data values, access is board dependent so must be configured. Valid 'zc706' or 'zc702' (default zc706) |
config | string | The configuratation file defining default values and Voltage Monitor names |
voutmode | int32 | Set the value to read for VOUT_MODE (default -12) |
statusmfrspecific | uns32 | Set the value to read for STATUS_MFR_SPECIFIC (default 0) |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
intOut | output | F (False) | Interrupt signal |
xadcmux | input | F (False) | Selects the channel for the XADC interface sample |
Bus Master Ports
This model has the following bus master ports:
Bus Master Port: xadc
Table 2: xadc
Name | Address Width (bits) | Description |
---|
xadc | 0 | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 3: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 4: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_CTRL | 0x0 | 32 | Control Register | | |
ab_LOCK | 0x4 | 32 | LOCK | | |
ab_CFG | 0x8 | 32 | Configuration Register | | |
ab_INT_STS | 0xc | 32 | Interrupt Status Register | | |
ab_INT_MASK | 0x10 | 32 | Interrupt Mask Register | | |
ab_STATUS | 0x14 | 32 | Status Register | | |
ab_DMA_SRC_ADDR | 0x18 | 32 | DMA Source address Register | | |
ab_DMA_DST_ADDR | 0x1c | 32 | DMA Destination address Register | | |
ab_DMA_SRC_LEN | 0x20 | 32 | DMA Source transfer Length Register | | |
ab_DMA_DEST_LEN | 0x24 | 32 | DMA Destination transfer Length Register | | |
ab_ROM_SHADOW | 0x28 | 32 | ROM_SHADOW | | |
ab_MULTIBOOT_ADDR | 0x2c | 32 | MULTI Boot Addr Pointer Register | | |
ab_UNLOCK | 0x34 | 32 | Unlock Register. The boot ROM will unlock the DEVCI by writing 0x757BDF0D to this register. | | |
ab_MCTRL | 0x80 | 32 | Miscellaneous control Register PS_VERSION=1 (v2.0 Silicon) | | |
ab_XADCIF_CFG | 0x100 | 32 | XADC Interface Configuration Register | | |
ab_XADCIF_INT_STS | 0x104 | 32 | XADC Interface Interrupt Status Register | | |
ab_XADCIF_INT_MASK | 0x108 | 32 | XADC Interface Interrupt Mask Register | | |
ab_XADCIF_MSTS | 0x10c | 32 | XADC Interface miscellaneous Status Register | | |
ab_XADCIF_CMDFIFO | 0x110 | 32 | XADC Interface Command FIFO Register | | |
ab_XADCIF_RDFIFO | 0x114 | 32 | XADC Interface Data FIFO Register | | |
ab_XADCIF_MCTL | 0x118 | 32 | XADC Interface Miscellaneous Control Register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 5: Publicly available platforms using peripheral 'zynq_7000-devcfg'