Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
abS_DSR | 0x0 | 32 | DMA Manager Status | | |
abS_DPC | 0x4 | 32 | DMA Program Counter | | |
abS_INTEN | 0x20 | 32 | DMASEV Instruction Response Control | | |
abS_INT_EVENT_RIS | 0x24 | 32 | Event Interrupt Raw Status | | |
abS_INTMIS | 0x28 | 32 | Interrupt Status | | |
abS_INTCLR | 0x2c | 32 | Interrupt Clear | | |
abS_FSRD | 0x30 | 32 | Fault Status DMA Manager | | |
abS_FSRC | 0x34 | 32 | Fault Status DMA Channel | | |
abS_FTRD | 0x38 | 32 | Fault Type DMA Manager | | |
abS_FTR0 | 0x40 | 32 | Default Type DMA Channel 0 | | |
abS_FTR1 | 0x44 | 32 | Default Type DMA Channel 1 | | |
abS_FTR2 | 0x48 | 32 | Default Type DMA Channel 2 | | |
abS_FTR3 | 0x4c | 32 | Default Type DMA Channel 3 | | |
abS_FTR4 | 0x50 | 32 | Default Type DMA Channel 4 | | |
abS_FTR5 | 0x54 | 32 | Default Type DMA Channel 5 | | |
abS_FTR6 | 0x58 | 32 | Default Type DMA Channel 6 | | |
abS_FTR7 | 0x5c | 32 | Default Type DMA Channel 7 | | |
abS_CSR0 | 0x100 | 32 | Channel Status DMA Channel 0 | | |
abS_CPC0 | 0x104 | 32 | Channel PC for DMA Channel 0 | | |
abS_CSR1 | 0x108 | 32 | Channel Status DMA Channel 1 | | |
abS_CPC1 | 0x10c | 32 | Channel PC for DMA Channel 1 | | |
abS_CSR2 | 0x110 | 32 | Channel Status DMA Channel 2 | | |
abS_CPC2 | 0x114 | 32 | Channel PC for DMA Channel 2 | | |
abS_CSR3 | 0x118 | 32 | Channel Status DMA Channel 3 | | |
abS_CPC3 | 0x11c | 32 | Channel PC for DMA Channel 3 | | |
abS_CSR4 | 0x120 | 32 | Channel Status DMA Channel 4 | | |
abS_CPC4 | 0x124 | 32 | Channel PC for DMA Channel 4 | | |
abS_CSR5 | 0x128 | 32 | Channel Status DMA Channel 5 | | |
abS_CPC5 | 0x12c | 32 | Channel PC for DMA Channel 5 | | |
abS_CSR6 | 0x130 | 32 | Channel Status DMA Channel 6 | | |
abS_CPC6 | 0x134 | 32 | Channel PC for DMA Channel 6 | | |
abS_CSR7 | 0x138 | 32 | Channel Status DMA Channel 7 | | |
abS_CPC7 | 0x13c | 32 | Channel PC for DMA Channel 7 | | |
abS_SAR0 | 0x400 | 32 | Source Address DMA Channel 0 | | |
abS_DAR0 | 0x404 | 32 | Destination Addr DMA Channel 0 | | |
abS_CCR0 | 0x408 | 32 | Channel Control DMA Channel 0 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200) | | |
abS_LC0_0 | 0x40c | 32 | Loop Counter 0 DMA Channel 0 | | |
abS_LC1_0 | 0x410 | 32 | Loop Counter 1 DMA Channel 0 | | |
abS_SAR1 | 0x420 | 32 | Source address DMA Channel 1 | | |
abS_DAR1 | 0x424 | 32 | Destination Addr DMA Channel 1 | | |
abS_CCR1 | 0x428 | 32 | Channel Control DMA Channel 1 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 ) | | |
abS_LC0_1 | 0x42c | 32 | Loop Counter 0 DMA Channel 1 | | |
abS_LC1_1 | 0x430 | 32 | Loop Counter 1 DMA Channel 1 | | |
abS_SAR2 | 0x440 | 32 | Source Address DMA Channel 2 | | |
abS_DAR2 | 0x444 | 32 | Destination Addr DMA Channel 2 | | |
abS_CCR2 | 0x448 | 32 | Channel Control DMA Channel 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 ) | | |
abS_LC0_2 | 0x44c | 32 | Loop Counter 0 DMA Channel 2 | | |
abS_LC1_2 | 0x450 | 32 | Loop Counter 1 DMA Channel 2 | | |
abS_SAR3 | 0x460 | 32 | Source Address DMA Channel 3 | | |
abS_DAR3 | 0x464 | 32 | Destination Addr DMA Channel 3 | | |
abS_CCR3 | 0x468 | 32 | Channel Control DMA Channel 3 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200) | | |
abS_LC0_3 | 0x46c | 32 | Loop Counter 0 DMA Channel 3 | | |
abS_LC1_3 | 0x470 | 32 | Loop Counter 1 DMA Channel 3 | | |
abS_SAR4 | 0x480 | 32 | Source Address DMA Channel 4 | | |
abS_DAR4 | 0x484 | 32 | Destination Addr DMA Channel 4 | | |
abS_CCR4 | 0x488 | 32 | Channel Control DMA Channel 4 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 ) | | |
abS_LC0_4 | 0x48c | 32 | Loop Counter 0 DMA Channel 4 | | |
abS_LC1_4 | 0x490 | 32 | Loop Counter 1 DMA Channel 4 | | |
abS_SAR5 | 0x4a0 | 32 | Source Address DMA Channel 5 | | |
abS_DAR5 | 0x4a4 | 32 | Destination Addr DMA Channel 5 | | |
abS_CCR5 | 0x4a8 | 32 | Channel Control DMA Channel 5 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 ) | | |
abS_LC0_5 | 0x4ac | 32 | Loop Counter 0 DMA Channel 5 | | |
abS_LC1_5 | 0x4b0 | 32 | Loop Counter 1 DMA Channel 5 | | |
abS_SAR6 | 0x4c0 | 32 | Source Address DMA Channel 6 | | |
abS_DAR6 | 0x4c4 | 32 | Destination Addr DMA Channel 6 | | |
abS_CCR6 | 0x4c8 | 32 | Channel Control DMA Channel 6 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 ) | | |
abS_LC0_6 | 0x4cc | 32 | Loop Counter 0 DMA Channel 6 | | |
abS_LC1_6 | 0x4d0 | 32 | Loop Counter 1 DMA Channel 6 | | |
abS_SAR7 | 0x4e0 | 32 | Source Address DMA Channel 7 | | |
abS_DAR7 | 0x4e4 | 32 | Destination Addr DMA Channel 7 | | |
abS_CCR7 | 0x4e8 | 32 | Channel Control DMA Channel 7 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 ) | | |
abS_LC0_7 | 0x4ec | 32 | Loop Counter 0 DMA Channel 7 | | |
abS_LC1_7 | 0x4f0 | 32 | Loop Counter 1 DMA Channel 7 | | |
abS_DBGSTATUS | 0xd00 | 32 | DMA Manager Execution Status | | |
abS_DBGCMD | 0xd04 | 32 | DMA Manager Instr. command | | |
abS_DBGINST0 | 0xd08 | 32 | DMA Manager Instruction Part A | | |
abS_DBGINST1 | 0xd0c | 32 | DMA Manager Instruction Part B | | |
abS_CR0 | 0xe00 | 32 | Config. 0: Events, Peripheral Interfaces, PC, Mode (dmac0_ns: 0x00000000 dmac0_s: 0x001E3071 ) | | |
abS_CR1 | 0xe04 | 32 | Config. 1: Instruction Cache (dmac0_ns: 0x00000000 dmac0_s: 0x00000074 ) | | |
abS_CR2 | 0xe08 | 32 | Config. 2: DMA Mgr Boot Addr | | |
abS_CR3 | 0xe0c | 32 | Config. 3: Security state of IRQs | | |
abS_CR4 | 0xe10 | 32 | Config 4, Security of Periph Interfaces | | |
abS_CRD | 0xe14 | 32 | DMA configuration (dmac0_ns: 0x00000000 dmac0_s: 0x07FF7F73 ) | | |
abS_WD | 0xe80 | 32 | Watchdog Timer | | |
abS_periph_id_0 | 0xfe0 | 32 | Peripheral Identification register 0 (dmac0_ns: 0x00000000 dmac0_s: 0x00000030 ) | | |
abS_periph_id_1 | 0xfe4 | 32 | Peripheral Identification register 1 (dmac0_ns: 0x00000000 dmac0_s: 0x00000013 ) | | |
abS_periph_id_2 | 0xfe8 | 32 | Peripheral Identification register 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00000024 ) | | |
abS_periph_id_3 | 0xfec | 32 | Peripheral Identification register 3 | | |
abS_pcell_id_0 | 0xff0 | 32 | Component Identification register 0 (dmac0_ns: 0x00000000 dmac0_s: 0x0000000D) | | |
abS_pcell_id_1 | 0xff4 | 32 | Component Identification register 1 (dmac0_ns: 0x00000000 dmac0_s: 0x000000F0) | | |
abS_pcell_id_2 | 0xff8 | 32 | Component Identification register 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00000005) | | |
abS_pcell_id_3 | 0xffc | 32 | Component Identification register 3 (dmac0_ns: 0x00000000 dmac0_s: 0x000000B1) | | |