Name | Offset | Width (bits) | Description | R/W | is Volatile |
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REG_MASK_DATA_0_LSW | 0x0 | 32 | Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) | | |
REG_MASK_DATA_0_MSW | 0x4 | 32 | Maskable Output Data (GPIO Bank0, MIO, Upper 16bits) | | |
REG_MASK_DATA_1_LSW | 0x8 | 32 | Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) | | |
REG_MASK_DATA_1_MSW | 0xc | 32 | Maskable Output Data (GPIO Bank1, MIO, Upper 6bits) | | |
REG_MASK_DATA_2_LSW | 0x10 | 32 | Maskable Output Data (GPIO Bank2, EMIO, Lower 16bits) | | |
REG_MASK_DATA_2_MSW | 0x14 | 32 | Maskable Output Data (GPIO Bank2, EMIO, Upper 16bits) | | |
REG_MASK_DATA_3_LSW | 0x18 | 32 | Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits) | | |
REG_MASK_DATA_3_MSW | 0x1c | 32 | Maskable Output Data (GPIO Bank3, EMIO, Upper 16bits) | | |
REG_DATA_0 | 0x40 | 32 | Output Data (GPIO Bank0, MIO) | | |
REG_DATA_1 | 0x44 | 32 | Output Data (GPIO Bank1, MIO) | | |
REG_DATA_2 | 0x48 | 32 | Output Data (GPIO Bank2, EMIO) | | |
REG_DATA_3 | 0x4c | 32 | Output Data (GPIO Bank3, EMIO) | | |
REG_DIRM_0 | 0x204 | 32 | Direction mode (GPIO Bank0,MIO) | | |
REG_OEN_0 | 0x208 | 32 | Output enable (GPIO Bank0,MIO) | | |
REG_INT_MASK_0 | 0x20c | 32 | Interrupt Mask Status (GPIO Bank0, MIO) | | |
REG_INT_EN_0 | 0x210 | 32 | Interrupt Enable/Unmask (GPIO Bank0, MIO) | | |
REG_INT_DIS_0 | 0x214 | 32 | Interrupt Disable/Mask (GPIO Bank0, MIO) | | |
REG_INT_STAT_0 | 0x218 | 32 | Interrupt Status (GPIO Bank0, MIO) | | |
REG_INT_TYPE_0 | 0x21c | 32 | Interrupt Type (GPIO Bank0, MIO) | | |
REG_INT_POLARITY_0 | 0x220 | 32 | Interrupt Polarity (GPIO Bank0, MIO) | | |
REG_INT_ANY_0 | 0x224 | 32 | Interrupt Any Edge Sensitive (GPIO Bank0, MIO) | | |
REG_DIRM_1 | 0x244 | 32 | Direction mode (GPIO Bank1, MIO) | | |
REG_OEN_1 | 0x248 | 32 | Output enable (GPIO Bank1, MIO) | | |
REG_INT_MASK_1 | 0x24c | 32 | Interrupt Mask Status (GPIO Bank1, MIO) | | |
REG_INT_EN_1 | 0x250 | 32 | Interrupt Enable/Unmask (GPIO Bank1, MIO) | | |
REG_INT_DIS_1 | 0x254 | 32 | Interrupt Disable/Mask (GPIO Bank1, MIO) | | |
REG_INT_STAT_1 | 0x258 | 32 | Interrupt Status (GPIO Bank1, MIO) | | |
REG_INT_TYPE_1 | 0x25c | 32 | Interrupt Type (GPIO Bank1, MIO) | | |
REG_INT_POLARITY_1 | 0x260 | 32 | Interrupt Polarity (GPIO Bank1, MIO) | | |
REG_INT_ANY_1 | 0x264 | 32 | Interrupt Any Edge Sensitive (GPIO Bank1, MIO) | | |
REG_DIRM_2 | 0x284 | 32 | Direction mode (GPIO Bank2, EMIO) | | |
REG_OEN_2 | 0x288 | 32 | Output enable (GPIO Bank2, EMIO) | | |
REG_INT_MASK_2 | 0x28c | 32 | Interrupt Mask Status (GPIO Bank2, EMIO) | | |
REG_INT_EN_2 | 0x290 | 32 | Interrupt Enable/Unmask (GPIO Bank2, EMIO) | | |
REG_INT_DIS_2 | 0x294 | 32 | Interrupt Disable/Mask (GPIO Bank2, EMIO) | | |
REG_INT_STAT_2 | 0x298 | 32 | Interrupt Status (GPIO Bank2, EMIO) | | |
REG_INT_TYPE_2 | 0x29c | 32 | Interrupt Type (GPIO Bank2, EMIO) | | |
REG_INT_POLARITY_2 | 0x2a0 | 32 | Interrupt Polarity (GPIO Bank2, EMIO) | | |
REG_INT_ANY_2 | 0x2a4 | 32 | Interrupt Any Edge Sensitive (GPIO Bank2, EMIO) | | |
REG_DIRM_3 | 0x2c4 | 32 | Direction mode (GPIO Bank3, EMIO) | | |
REG_OEN_3 | 0x2c8 | 32 | Output enable (GPIO Bank3, EMIO) | | |
REG_INT_MASK_3 | 0x2cc | 32 | Interrupt Mask Status (GPIO Bank3, EMIO) | | |
REG_INT_EN_3 | 0x2d0 | 32 | Interrupt Enable/Unmask (GPIO Bank3, EMIO) | | |
REG_INT_DIS_3 | 0x2d4 | 32 | Interrupt Disable/Mask (GPIO Bank3, EMIO) | | |
REG_INT_STAT_3 | 0x2d8 | 32 | Interrupt Status (GPIO Bank3, EMIO) | | |
REG_INT_TYPE_3 | 0x2dc | 32 | Interrupt Type (GPIO Bank3, EMIO) | | |
REG_INT_POLARITY_3 | 0x2e0 | 32 | Interrupt Polarity (GPIO Bank3, EMIO) | | |
REG_INT_ANY_3 | 0x2e4 | 32 | Interrupt Any Edge Sensitive (GPIO Bank3, EMIO) | | |