OVP Peripheral Model: XilinxZynq7000Iic
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Zynq 7000 I2C Registers. This model also includes the behaviour for PCA9548 I2C Bus Switch
Licensing
Open Source Apache 2.0
Limitations
This model implements the full set of registers and behaviour to read and write the I2C address space.
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf).
Evaluation Board ZC706 (ug954-zc706-eval-board-xc7z045-ap-soc.pdf)
Evaluation Board ZC702 (ug850-zc702-eval-board.pdf)
Location
The zynq_7000-iic peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-iic / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
PCLK | uns32 | The Peripheral clock frequency in MHz (default 133 MHz) |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
intOut | output | F (False) | |
Bus Master Ports
This model has the following bus master ports:
Bus Master Port: I2C_Master
Table 2: I2C_Master
Name | Address Width (bits) | Description |
---|
I2C_Master | 10 | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: I2C_Slave
Table 3: Bus Slave Port: I2C_Slave
Name | Size (bytes) | Must Be Connected | Description |
---|
I2C_Slave | 0x4 | F (False) | |
No address blocks have been defined for this slave port.
Bus Slave Port: bport1
Table 4: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 5: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_Control | 0x0 | 32 | Control register | | |
ab_I2CAddress | 0x8 | 32 | I2C Address register | | |
ab_I2CData | 0xc | 32 | I2C Data register | | |
ab_TransferSize | 0x14 | 32 | Transfer Size register | | |
ab_SlaveMonPause | 0x18 | 32 | Slave Monitor Pause register | | |
ab_TimeOut | 0x1c | 32 | Time Out register | | |
ab_InterruptMask | 0x20 | 32 | Interrupt Mask register | | |
ab_InterruptEnable | 0x24 | 32 | Interrupt Enable register | | |
ab_InterruptDisable | 0x28 | 32 | Interrupt Disable register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 6: Publicly available platforms using peripheral 'zynq_7000-iic'