OVP Peripheral Model: XilinxZynq7000Ocm
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Zynq 7000 Platform On Chip Memory Controller Registers (OCM)
Licensing
Open Source Apache 2.0
Limitations
This model implements the full set of registers. There is no behavior included.
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
Location
The zynq_7000-ocm peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-ocm / 1.0.
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table : Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 1: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_OCM_PARITY_CTRL | 0x0 | 32 | Control fields for RAM parity operation | | |
ab_OCM_PARITY_ERRADDRESS | 0x4 | 32 | Stores the first parity error access address. This register is sticky and will retain its value unless explicitly cleared (written with 1's) with an APB write access. The physical RAM address is logged. | | |
ab_OCM_IRQ_STS | 0x8 | 32 | Status of OCM Interrupt | | |
ab_OCM_CONTROL | 0xc | 32 | Control fields for OCM | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 2: Publicly available platforms using peripheral 'zynq_7000-ocm'