OVP Peripheral Model: XilinxZynq7000Qspi
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Zynq 7000 Quad-SPI Registers and incorporates Flash Memory (Spansion and Micron) for Zync zc702/zc706 boards
Licensing
Open Source Apache 2.0
Limitations
This model implements the full set of registers but not all flash memory accesses are supported.
The model is tested using Xilinx Example Project for R/W a QPSI memory on ZC702 platform using Polled and Interrupt driven Transfers. https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/qspips/examples
The AXI mode of operation is not tested. There is no write protection implemented for memory access when in AXI mode.
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
https://xilinx.github.io/embeddedsw.github.io/qspips/doc/html/api/index.html
Location
The zynq_7000-qspi peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-qspi / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
image | string | Specify a file to initialize flash memory. String of form <file>[@<offset>] |
imageout | string | Specify a file to write the flash memory at the end of simulation. String of form <file>[@<offset>][:<size>] |
flash | string | Description Specify the type of flash memory, 'spansion' or 'micron' (default) Limitations The Spansion Flash memory device is not tested. The Micron flash memory device is tested using the Xilinx example program. |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
interrupt | output | F (False) | Interrupt signal |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bpAXI
Table 2: Bus Slave Port: bpAXI
Name | Size (bytes) | Must Be Connected | Description |
---|
bpAXI | 0x2000000 | T (True) | |
No address blocks have been defined for this slave port.
Bus Slave Port: bpAPB
Table 3: Bus Slave Port: bpAPB
Name | Size (bytes) | Must Be Connected | Description |
---|
bpAPB | 0x1000 | T (True) | |
Table 4: Bus Slave Port: bpAPB Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_Config_reg | 0x0 | 32 | QSPI configuration register | | |
ab_Intr_status_REG | 0x4 | 32 | QSPI interrupt status register | | |
ab_Intrpt_en_REG | 0x8 | 32 | Interrupt Enable register. | | |
ab_Intrpt_dis_REG | 0xc | 32 | Interrupt disable register. | | |
ab_Intrpt_mask_REG | 0x10 | 32 | Interrupt mask register | | |
ab_En_REG | 0x14 | 32 | SPI_Enable Register | | |
ab_Delay_REG | 0x18 | 32 | Delay Register | | |
ab_TXD0 | 0x1c | 32 | Transmit Data Register. Keyhole addresses for the Transmit data FIFO. See also TXD1-3. | | |
ab_Rx_data_REG | 0x20 | 32 | Receive Data Register | | |
ab_Slave_Idle_count_REG | 0x24 | 32 | Slave Idle Count Register | | |
ab_TX_thres_REG | 0x28 | 32 | TX_FIFO Threshold Register | | |
ab_RX_thres_REG | 0x2c | 32 | RX FIFO Threshold Register | | |
ab_GPIO | 0x30 | 32 | General Purpose Inputs and Outputs Register for the Quad-SPI Controller core | | |
ab_LPBK_DLY_ADJ | 0x38 | 32 | Loopback Master Clock Delay Adjustment Register | | |
ab_TXD1 | 0x80 | 32 | Transmit Data Register. Keyhole addresses for the Transmit data FIFO. | | |
ab_TXD2 | 0x84 | 32 | Transmit Data Register. Keyhole addresses for the Transmit data FIFO. | | |
ab_TXD3 | 0x88 | 32 | Transmit Data Register. Keyhole addresses for the Transmit data FIFO. | | |
ab_LQSPI_CFG | 0xa0 | 32 | Configuration Register specifically for the Linear Quad-SPI Controller | | |
ab_LQSPI_STS | 0xa4 | 32 | Status Register specifically for the Linear Quad-SPI Controller | | |
ab_MOD_ID | 0xfc | 32 | Module Identification register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 5: Publicly available platforms using peripheral 'zynq_7000-qspi'