OVP Peripheral Model: XilinxZynq7000Spi
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Zynq 7000 SPI Registers
Licensing
Open Source Apache 2.0
Limitations
This model implements the full set of registers but no behavior.
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
Location
The zynq_7000-spi peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-spi / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
intOut | output | F (False) | Interrupt signal |
Bus Master Ports
This model has the following bus master ports:
Bus Master Port: SPI
Table 1: SPI
Name | Address Width (bits) | Description |
---|
SPI | 32 | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 3: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_Config | 0x0 | 32 | SPI configuration register | | |
ab_Intr_status | 0x4 | 32 | SPI interrupt status register | | |
ab_Intrpt_en | 0x8 | 32 | Interrupt Enable register | | |
ab_Intrpt_dis | 0xc | 32 | Interrupt disable register | | |
ab_Intrpt_mask | 0x10 | 32 | Interrupt mask register | | |
ab_En | 0x14 | 32 | SPI_Enable Register | | |
ab_Delay | 0x18 | 32 | Delay Register | | |
ab_Tx_data | 0x1c | 32 | Transmit Data Register. | | |
ab_Rx_data | 0x20 | 32 | Receive Data Register | | |
ab_Slave_Idle_count | 0x24 | 32 | Slave Idle Count Register | | |
ab_TX_thres | 0x28 | 32 | TX_FIFO Threshold Register | | |
ab_RX_thres | 0x2c | 32 | RX FIFO Threshold Register | | |
ab_Mod_id | 0xfc | 32 | Module ID register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'zynq_7000-spi'