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ZynqPLTTELNoCprocessingnodepublicdemonstrator



OVP Virtual Platform: Zynq_PL_TTELNoC_processing_node_public_demonstrator

This page provides detailed information about the OVP Virtual Platform Model of the safepower.ovpworld.org Zynq_PL_TTELNoC_processing_node_public_demonstrator platform.

Licensing

Open Source Apache 2.0

Description

This module implements a Processing Node for the SafePower Public Demonstrator in the Xilinx Zynq Programmable Logic (PL). This PL configuration instances one Xilinx MicroBlaze processor with a local memory and a TTEL NoC interface peripheral.

Limitations

Provides a baremetal implementation.

Reference

SafePower Public Demonstrator

Location

The Zynq_PL_TTELNoC_processing_node_public_demonstrator virtual platform is located in an Imperas/OVP installation at the VLNV: safepower.ovpworld.org / module / Zynq_PL_TTELNoC_processing_node_public_demonstrator / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorcpuxilinx.ovpworld.orgmicroblaze
Peripheralnisafepower.ovpworld.orgTTELNode
Peripheralintcxilinx.ovpworld.orgaxi-intc
Peripheraltimerxilinx.ovpworld.orgaxi-timer
MemoryramSovpworld.orgram
Memorydebug_gpioovpworld.orgram
Memoryaxi_gpioovpworld.orgram
Memoryclock_controlovpworld.orgram
Memoryttel_clockovpworld.orgram
BuspBus(builtin)address width:32

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module Zynq_PL_TTELNoC_processing_node_public_demonstrator

Table 2: External Ports

Port TypePort NameInternal Connection
packetnetportnetworkNodePortnetworkNode



Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: cpu

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
mips100The nominal MIPS for the processor

Table 4: Processor Instance 'cpu' Parameters (Attributes)

Parameter NameValueType
C_ENDIANNESS1uns32
C_USE_INTERRUPT1uns32
C_INTERCONNECT2uns32
C_USE_FPU1uns32
C_USE_HW_MUL2uns32
C_USE_DIV1boolean

Memory Map for processor 'cpu' bus: 'pBus'

Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.

Table 5: Memory Map ( 'cpu' / 'pBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFramSram
0x400000000x4000FFFFdebug_gpioram
0x400300000x4003FFFFaxi_gpioram
0x412000000x412001FFintcaxi-intc
0x41C000000x41C0001Ftimeraxi-timer
0x44A300000x44A3FFFFclock_controlram
0x44A400000x44A4FFFFttel_clockram
0x800000000x80FFFFFFniTTELNode

Net Connections to processor: 'cpu'

Table 6: Processor Net Connections ( 'cpu' )

Net PortNetInstanceComponent
Interruptintc_mbintcaxi-intc



Peripheral Instances



Peripheral [safepower.ovpworld.org/peripheral/TTELNode/1.0] instance: ni

Description

The TTEL Network on Chip (NoC) node peripheral for SafePower Project

Licensing

Open Source Apache 2.0

Limitations

This model implements the TTEL NoC node processor interface. It does not model any timing in the transfer of messages between nodes.

Reference

Generated using document TTEL Software Extensions ver 1.0 and D1.2.1 architectural style of dreams r1-0.

Table 7: Configuration options (attributes) set for instance 'ni'

AttributesValue
clustercluster
tiletile
nodenode



Peripheral [xilinx.ovpworld.org/peripheral/axi-intc/1.0] instance: intc

Description

Microblaze LogiCORE IP AXI Interrupt Controller

Licensing

Open Source Apache 2.0

Limitations

Implements the basic interrupt processing behavior
Does not implement interrupt cascade

Reference

PG099 October 4, 2017 v4.1

There are no configuration options set for this peripheral instance.



Peripheral [xilinx.ovpworld.org/peripheral/axi-timer/1.0] instance: timer

Description

Xilinx AXI Timer

Licensing

Open Source Apache 2.0

Limitations

Resolution of this timer is limited to the simulation time slice (aka quantum) size

Reference

pg079-axi-timer, Vivado Design Suite, October t, 2016

Table 8: Configuration options (attributes) set for instance 'timer'

AttributesValue
endianlittle
frequency100.000000




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