Uses  OVP ARM Integrator platform,  OVP ARM processor models and OCP-IP SystemC TLM Modeling kit

Open Core Protocol International Partnership (OCP-IP), the organization delivering a common standard for intellectual property core interfaces that facilitate “plug and play” SoC design, and CircuitSutra, experts in SystemC modeling and embedded software development, along with Imperas, the company providing the infrastructure for the future of software virtual platforms and enabling the next generation of embedded software development, today announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit. This example platform acts as a guide to OCP-IP members enabling them to quick-start their ESL activities using the OCP-IP TLM Modeling Kit; which is fully compatible with OSCI’s TLM 2.0.1. Both the kit and Virtual Platform examples are free to both OCP-IP members and non-members.

The Virtual Platform Demo utilizes Open Virtual Platforms (OVP) technology…

For more information, please read the full press release here, or download it here.

You can get the virtual platform here, and see the OVP information here and here.

For the CircuitSutra presentation on the virtual platform visit here.

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Richard Goering Interviews Simon Davidmann at DAC2010

Imperas has been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions. Simon Davidmann, Imperas CEO, talked about that work in a Cadence Design Automation Conference 2010 booth presentation, and continued the discussion afterwards in a video interview.

Imperas has taken an unusual approach to the virtual platform market - it offers models and much of its simulation and prototyping technology available for free, through the Open Virtual Platforms (OVP) initiative. Imperas also provides technology that makes it possible to analyze what’s going on in the models at run time.

To read the article and to watch the video interview please visit the Cadence site here.

To watch the video interview on YouTube go here.

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Conference Coverage - Gary Smith at DVCon San Jose, March 2010, an article by  Bill Murray at www.SCDsource.com

Gary Smith of GarySmithEDA presented a snapshot of the status and direction of electronic system level design (ESL) methodology at the recent Open SystemC Initiative (OSCI) SystemC day at the Design and Verification Conference (DVCon 2010) in San Jose, California. He talked about the progress of ESL, its five high value applications, market sizing and concluded with some comments about its ability to satisfy the needs of the embedded system software developer.
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Smith said “We have two killer apps down. One is ESL synthesis. …

The other one is the software virtual prototype. Synopsys has just bought nearly everyone, but Carbon and Imperas remain.”
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To read the full article, please visit http://www.scdsource.com/article.php?id=386.

SUNNYVALE, Calif. - November 2, 2009 - MIPS Technologies, Inc. (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores, today introduced a new core family providing the highest levels of system performance for extremely cost-sensitive embedded applications such as 32-bit microcontrollers (MCUs), home entertainment, personal entertainment and home networking. The new MIPS32® M14KTM and M14KcTM cores are the first MIPS32-compatible cores that also execute the new microMIPSTM instruction set architecture (ISA), achieving high performance of
1.5 DMIPS/MHz with an advanced level of code compression. The microMIPS ISA maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant …

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Software developers can also take advantage of fast instruction set simulators developed in conjunction with Imperas for use in software development and virtual platforms.
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“We are working together with MIPS to create MIPS-VerifiedTM instruction-accurate models of its newest cores that MIPS will provide to its licensees,” said Simon Davidmann, CEO of Imperas. “With our instruction accurate simulation technology and these models, developers can simulate complete embedded systems running real application code at very fast speeds on typical desktop PCs-helping them get to market quickly at the lowest possible cost.”
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For full text of the release, please read the release on the MIPS site.

VinChip offers India-developed 32-bit RISC processor

Peter Clarke, (EETimes)
(06/22/2009 6:42 AM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=218100501

LONDON — VinChip Systems Inc. (San Jose, Calif.) has announced the availability of the VinRZ5110 32-bit RISC processor core, which it claims is the first 32-but processor to be developed in India. It has a DSP-centric instruction set and low gate count for low power consumption, the company said.

VinChip, which has a design center in Chennai, India, said the VinRZ5110 is suitable for use in applications including mass storage, automotive control, wireless devices and audio/video encoders and decoders. It is also suitable for FPGA-based embedded systems.

The core has been developed with on-chip debug logic based on OpenOCD, which also supports in-system programming via JTAG. An optional module, the VinSMDP, provides static and dynamic capture of debug data and in-system programming over USB 2.0 achieving speeds of 480-Mbits per second. The VinSMDP can also multi-task as a USB port for user tasks on the AHB bus.

The VinRZ5110 core has…

[For the full article read here]

[For the VinChip press release go here]

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, has announced its System-Level Catalyst Program to accelerate the adoption of system-level design and verification.

Imperas is a founding charter member, joining at the program’s creation. “The integration of Open Virtual Platforms (OVP) processor models with the Synopsys Innovator tools provides customers with an expanded set of IP with which to build virtual platforms. Moreover, the native TLM-2.0 interface in the instruction accurate OVP models ensures that users will have the fastest possible simulation performance, as is required for software development on virtual platforms, ” said Simon Davidmann, Imperas CEO.

System-Level Catalyst Program is designed to benefit mutual customers by advancing tool and model interoperability as well as availability of system-level models and services.

The members of the program include Synopsys, Imperas, and many other supporters of the Open Virtual Platforms initiative, including: Carbon, CriticalBlue, Doulos, Forte, GreenSocs, and Tensilica.

[For more information, please see the Synopsys press release here]