OVP represented on lively lunchtime panel at DAC Virtual Platform Workshop in San Francisco

Last week at the 46th Design Automation Conference there was a workshop on Virtual Platforms.

The workshop began with a tutorial-like state-of-the-art overview on critical issues facing VP developers and users. The morning session then continued with detailed presentations on building VPs: exploring timing mechanisms in TLM (Transaction-Level Modeling), integration of RTL Models into Virtual Platforms for complex multicore systems, and platform composition and refinement. Speakers were from Qualcomm, Inc., Brian Bailey Consulting, Carbon Design Systems, Inc., FZI Karlsruhe, and EVE.

The lunch time panel session was lively, interesting and brought several industry experts together to discuss issues facing virtual platform designers and users such as software reuse, status of VP standards, and how and when VPs will achieve broader acceptance. The panelists were from ARM, Qualcomm, GreenSocs, Open Virtual Platforms (OVP), and Cadence Design Systems, Inc. The lunch panel was moderated by Michael Sanie, Maestro Intl., Menlo Park, CA.

The afternoon session consisted of six industry experts introducing tools and experiences in: software functional verification, architectural exploration on VPs, combining TLM-2.0 code with legacy virtual platforms, and system verification. The speakers were from CoWare, Inc., Intel Corp., Posedge Software, Imperas Ltd., Mentor Graphics, and Synopsys, Inc.

To find out more about the workshop and to have a look at the slides presented by the contributors, please visit here.