The MIPS I7200 is the first core in the MIPS lineup to implement the nanoMIPS instruction set architecture (ISA), a new version of MIPS ISA designed to deliver best in class small code size, but without sacrificing the high performance required in todays applications. When compiled for performance (-O3 compile flag), nanoMIPS can achieve ~ 40% smaller code size than standard MIPS32.
The MIPS I6400 multiprocessor core is a compelling new licensable IP core in MIPS CPU product line, bringing the proven and respected MIPS64 architecture and a suite of key new features and capabilities to a wide range of markets and applications. The I6400 is the most recent member of the Warrior generation of MIPS CPU cores and is a major step forward as the next generation of the MIPS mid-range I-Class product line. It achieves new performance/efficiency levels and incorporates compelling new features such as simultaneous multi-threading (SMT), hardware virtualization, 128-bit SIMD, advanced power management, multi-context security, and extensibility to coherent multi-cluster operation.

Processor Model Variants of MIPS / Warrior / I-Class