The minimum, mandatory set of RISC-V instructions is the integer instruction set. (Indicated with a letter 'I'.)
This set by itself can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler. A computer design may add further subsets: Integer multiplication and division (set 'M'),
Atomic instructions for handling real-time concurrency (A'),
IEEE Floating point ('F') with Double-precision ('D') and Quad-precision ('Q') options.

A 'privileged' instruction set defines instructions to support a UNIX-style operating system.

There are plans for it to support hypervisors, to support virtualization.
A computer with all of these instruction sets, an 'RVIAFDP' is said to be 'general-purpose' summarized as 'G'.
There is an optional 'compact' subset to reduce code size (set 'C'). Many RISC-V computers might add this ISA to reduce power, code size, and memory.

There is also a 32-bit embedded subset ('E') that supports only 16 registers, to reduce the cost of the smallest CPUs.

Thus a 32bit variant could be one of RV32I, RV32A, RV32F, RV32D, RV32P, RV32C, and RV32E.
And the 64bit ones instruction subsets are similar: RV64I, RV64A, RV64F, RV64D, RV64P, RV64C.
Time will tell what subsets will be most common/useful - please contact us if you need something currently not yet available.

Processor Model Variants of RISC-V / RISCV / RISCV