Content for OVP Fast Processor Model Variant: Altera Nios II / Nios_II_S

APPLICATION NOTES
(more docs)

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Altera Nios II Nios_II_S


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas Altera Nios II Nios_II_S ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The Altera Nios II Nios_II_S ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of Altera Nios II Nios_II_S Fast Processor Model


Model Variant name: Nios_II_S
Description:
    Nios_II Family Processor Model.
Licensing:
    Open Source Apache 2.0
Limitations:
    No Custom instructions.
    No Cache model.
    No JTAG.
    
Verification:
    Models have been extensively tested by Imperas, and validated against tests from Altera.
Features:
    Barrel Shifter.
    Hardware Multiply.
    Hardware Divide.

Model downloadable (needs registration and to be logged in) in package Nios_II.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant Nios_II_S is available OVP_Model_Specific_Information_nios_ii_Nios_II_S.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: altera.ovpworld.org/processor/nios_ii/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x71
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 32
master DATA 32

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset_n input
d_irq0 input
d_irq1 input
d_irq2 input
d_irq3 input
d_irq4 input
d_irq5 input
d_irq6 input
d_irq7 input
d_irq8 input
d_irq9 input
d_irq10 input
d_irq11 input
d_irq12 input
d_irq13 input
d_irq14 input
d_irq15 input
d_irq16 input
d_irq17 input
d_irq18 input
d_irq19 input
d_irq20 input
d_irq21 input
d_irq22 input
d_irq23 input
d_irq24 input
d_irq25 input
d_irq26 input
d_irq27 input
d_irq28 input
d_irq29 input
d_irq30 input
d_irq31 input

No FIFO Ports in Nios_II_S.


Exceptions


Name Code Description
NONE 0
RESET 1
HARDWARE_BREAK 2
PROCESSOR_ONLY_RESET_REQUEST 4
INTERNAL_INTERRUPT 8
EXTERNAL_NONMASKABLE_INTERRUPT 16
EXTERNAL_MASKABLE_INTERRUPT 32
SUPERVISOR_ONLY_INSTRUCTION_ADDRESS 64
FAST_TLB_MISS_INSTRUCTION 128
DOUBLE_TLB_MISS_INSTRUCTION 256
TLB_PERMISSION_VIOLATION_EXECUTE 512
MPU_REGION_VIOLATION_INSTRUCTION 1024
SUPERVISOR_ONLY_INSTRUCTION 2048
TRAP_INSTRUCTION 4096
ILLEGAL_INSTRUCTION 8192
UNIMPLEMENTED_INSTRUCTION 16384
BREAK_INSTRUCTION 32768
SUPERVISOR_ONLY_DATA_ADDRESS 65536
MISALIGNED_DATA_ADDRESS 131072
MISALIGNED_DESTINATION_ADDRESS 262144
DIVISION_ERROR 524288
FAST_TLB_MISS_DATA 1048576
DOUBLE_TLB_MISS_DATA 2097152
TLB_PERMISSION_VIOLATION_READ 4194304
TLB_PERMISSION_VIOLATION_WRITE 8388607
MPU_REGION_VIOLATION_DATA 8388607

Execution Modes


Mode Code Description
VM_MODE_KERNEL 0
VM_MODE_USER 1
VM_MODE_KERNEL_MPU 2
VM_MODE_USER_MPU 3

More Detailed Information

The Nios_II_S OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_nios_ii_Nios_II_S.pdf.

Other Sites/Pages with similar information

Information on the Nios_II_S OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.