Content for OVP Fast Processor Model Variant: Andes / AX25F

APPLICATION NOTES
(more docs)
DOWNLOAD REFERENCE/DEMO PLATFORMS

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Andes AX25F


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas Andes AX25F ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The Andes AX25F ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of Andes AX25F Fast Processor Model


Model Variant name: AX25F
Description:
    RISC-V AX25F 64-bit processor model
Licensing:
    This Model is released under the Open Source Apache 2.0
Features:
    The model supports the following architectural features, defined in the misa CSR:
    extension A (atomic instructions)
    extension C (compressed instructions)
    extension D (double-precision floating point)
    extension F (single-precision floating point)
    RV32I/64I/128I base ISA
    extension M (integer multiply/divide instructions)
    extension S (Supervisor mode)
    extension U (User mode)
    extension X (non-standard extensions present)
    64-bit XLEN
    If required, supported architectural features may be overridden using parameter "misa_Extensions". Parameter "misa_Extensions_mask" can be used to specify which features can be dynamically enabled or disabled by writes to the misa register.
    On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
    Values written to "mtvec" are masked using the value 0xfffffffffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
    The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
    Values written to "stvec" are masked using the value 0xfffffffffffffffd. A different mask of writable bits may be specified using parameter "stvec_mask" if required. parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment in the same manner as for the "mtvec" register, described above.
    On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
    On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
    WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
    The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
    The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
    The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
    A 0-bit ASID is implemented. Use parameter "ASID_bits" to specify a different implemented ASID size if required.
    This variant supports address translation modes 0, 8 and 9. Use parameter "Sv_modes" to specify a bit mask of different modes if required.
    Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
    A PMP unit is not implemented by this variant. Set parameter "PMP_registers" to indicate that the unit should be implemented with that number of PMP entries.
    LR/SC instructions are implemented with a 1-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".
    By default, the processor starts with floating-point instructions disabled (mstatus.FS=0). Use parameter "mstatus_FS" to force mstatus.FS to a non-zero value for floating-point to be enabled from the start.
    The D extension is enabled in this variant independently of the F extension. Set parameter "d_requires_f"to "T" to specify that the D extension requires the F extension to be enabled.
    This variant implements floating point status in mstatus.FS as defined in the Privileged Architecture specification. To specify that a simpler mode supporting only values 0 (Off) and 3 (Dirty) should be used, Set parameter "fs_always_dirty" to "T". When this simpler mode is used, any write of values 1 (Initial) or 2 (Clean) from privileged code behave as if value 3 was written.
Interrupts:
    The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
    The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
    All other interrupt ports are active high.
Debug Mask:
    It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
    Value 0x002: enable debugging of PMP and virtual memory state;
    Value 0x004: enable debugging of interrupt state.
    All other bits in the debug bitmask are reserved and must not be set to non-zero values.
Integration Support:
    This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
CSR Register External Implementation:
    If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.
LR/SC Active Address:
    Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    The processor fully supports the architecturally-specified floating-point instructions with the exception of the round-to-nearest, ties-to-max-magnitude rounding mode (RMM) which is supported for fcvt instruction variants that convert to long, unsigned long, word, or unsigned word only. In other cases, this rounding mode is treated a round-to-nearest, ties-to-even (RNE). Use of RMM rounding mode in any situation other than rounding to an integral value is dubious because it leads to cumulative bias towards larger-magnitude values.
    Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.
    The TLB is architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.
    This variant is under development. It includes Supervisor mode and associated standard RISC-V features, but some Andes-specific CSRs are not yet implemented.
    Andes-specific cache, local memory and ECC behavior is not yet implemented, except for CSR state. Andes Performance and Code Dense instructions and associated CSR state are implemented, but the EXEC.IT instruction supports in-memory table mode using the uitb CSR only (not hardwired mode).
Verification:
    All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
References:
    The Model details are based upon the following specifications:
    ---- RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.2)
    ---- RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.10)
    ---- AndesCore_AX25_DS142_V1.1 DS142-11
    ---- AndeStar V5 Instruction Extension Specification (UMxxx-0.4, 2018-05-30)
    ---- AndeStar V5 Architecture and CSR Definitions (UM164-12, 2018-06-14)
Andes-Specific Extensions:
    Andes processors add various custom extensions to the basic RISC-V architecture. This model implements the following:
    1: Hardware Stack Protection (if mmsc_cfg.HSP=1);
    2: Performance Throttling (register interface only, if mmsc_cfg.PFT=1);
    3: CSRs for CCTL Operations (register interface only, if mmsc_cfg.CCTLCSR=1);
    4: Performance Extension instructions (if mmsc_cfg.EV5MPE=1);
    5: CodeDense instructions (if mmsc_cfg.ECD=1);
    6: Half-Precision Floating-Point instructions (if mmsc_cfg.EFHW=1).
    Other Andes-specific extensions are not currently modeled. The exact set of supported extensions can be configured using parameter "andesExtensions/mmsc_cfg", which overrides the default value of the mmsc_cfg register (see detailed description below).
Andes-Specific Parameters:
    In addition to the base model RISC-V parameters, this model implements parameters allowing Andes-specific model features to be controlled. These parameters are documented below.
Parameter andesExtensions/mmsc_cfg:
    This parameter allows the value of the read-only mmsc_cfg register to be specified. Bits that affect behavior of the model are:
    bit 3 (ECD): enables CodeDense instructions and uitb CSR.
    bit 4 (PFT): determines presence of mpft_ctl register and affects implemented fields in mxstatus.
    bit 5 (HSP): enables HW Stack protection, relevant CSRs and affects implemented fields in mxstatus.
    bit 13 (EV5PE): enables Performance Extension support.
    bit 16 (CCTLCSR): enables CCTL CSRs.
    Other bits can be set or cleared but do not affect model behavior.
    Example: --override iss/cpu0/andesExtensions/mmsc_cfg=0x2028
Parameter andesExtensions/micm_cfg:
    This parameter allows the value of the read-only micm_cfg register to be specified. Bits that affect behavior of the model are:
    bits 8:6 (ISZ): enables mcache_ctl CSR if non-zero.
    bits 14:12 (ILMB): enables milmb CSR if non-zero.
    Other bits can be set or cleared but do not affect model behavior, except that if any bit is non zero then IME/PIME bits in mxstatus are modeled.
    Example: --override iss/cpu0/andesExtensions/micm_cfg=0
Parameter andesExtensions/mdcm_cfg:
    This parameter allows the value of the read-only mdcm_cfg register to be specified. Bits that affect behavior of the model are:
    bits 8:6 (DSZ): enables mcache_ctl CSR if non-zero.
    bits 14:12 (DLMB): enables mdlmb CSR if non-zero.
    Other bits can be set or cleared but do not affect model behavior, except that if any bit is non zero then DME/DIME bits in mxstatus are modeled.
    Example: --override iss/cpu0/andesExtensions/mdcm_cfg=0
Parameter andesExtensions/uitb:
    This parameter allows the value of the uitb register to be specified.
    Example: --override iss/cpu0/andesExtensions/uitb=0
Parameter andesExtensions/milmb:
    This parameter allows the value of the milmb register to be specified.
    Example: --override iss/cpu0/andesExtensions/milmb=0
Parameter andesExtensions/milmbMask:
    This parameter allows the mask of writable bits in the milmb register to be specified. The default value for this variant is 0xe (RWECC and ECCEN are writable, all other bits are read-only).
    Example: --override iss/cpu0/andesExtensions/milmbMask=0xe
Parameter andesExtensions/mdlmb:
    This parameter allows the value of the mdlmb register to be specified.
    Example: --override iss/cpu0/andesExtensions/mdlmb=0
Parameter andesExtensions/mdlmbMask:
    This parameter allows the mask of writable bits in the mdlmb register to be specified. The default value for this variant is 0xe (RWECC and ECCEN are writable, all other bits are read-only).
    Example: --override iss/cpu0/andesExtensions/mdlmbMask=0xe
Hardware Stack Protection:
    Hardware Stack Protection is present on this variant (mmsc_cfg.HSP=1). Registers mhsp_ctl, msp_bound and msp_base are implemented.
Performance Throttling:
    Performance Throttling registers are present on this variant (mmsc_cfg.PFT=1). Register mpft_ctl is present but has no behavior except for the effects on mxstatus, which are modeled.
CSRs for CCTL Operations:
    CSRs for CCTL Operation are not present on this variant (mmsc_cfg.CCTLCSR=0).
Andes-Specific Instructions:
    This section describes Andes-specific instructions implemented by this variant. Refer to Andes reference documentation for more information.
Performance Extension Instructions:
    ADDIGP
    BBC
    BBS
    BEQC
    BNEC
    BFOS
    BFOZ
    LEA.h
    LEA.w
    LEA.d
    LEA.b.ze
    LEA.h.ze
    LEA.w.ze
    LEA.d.ze
    LBGP
    LBUGP
    LHGP
    LHUGP
    LWGP
    LWUGP
    LDGP
    SBGP
    SHGP
    SWGP
    SDGP
    FFB
    FFZMISM
    FFMISM
    FLMISM
CodeDense Instructions:
    EXEC.IT
    EX9.IT
Half-Precision Floating-Point Instructions:
    FLHW
    FSHW

Model downloadable (needs registration and to be logged in) in package andes_riscv.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant AX25F is available OVP_Model_Specific_Information_andes_riscv_AX25F.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: andes.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 32
master DATA 32

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
nmi input
SSWInterrupt input
MSWInterrupt input
STimerInterrupt input
MTimerInterrupt input
SExternalInterrupt input
MExternalInterrupt input

No FIFO Ports in AX25F.


Exceptions


Name Code Description
InstructionAddressMisaligned 0
InstructionAccessFault 1
IllegalInstruction 2
Breakpoint 3
LoadAddressMisaligned 4
LoadAccessFault 5
StoreAMOAddressMisaligned 6
StoreAMOAccessFault 7
EnvironmentCallFromUMode 8
EnvironmentCallFromSMode 9
EnvironmentCallFromMMode 11
InstructionPageFault 12
LoadPageFault 13
StoreAMOPageFault 15
SSWInterrupt 65
MSWInterrupt 67
STimerInterrupt 69
MTimerInterrupt 71
SExternalInterrupt 73
MExternalInterrupt 75
HSP_OVF 32
HSP_UDF 33

Execution Modes


Mode Code Description
User 0
Supervisor 1
Machine 3

More Detailed Information

The AX25F OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_andes_riscv_AX25F.pdf.

Other Sites/Pages with similar information

Information on the AX25F OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.