Content for OVP Fast Processor Model Variant: MIPS / proAptiv

APPLICATION NOTES
(more docs)

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS proAptiv


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas MIPS proAptiv ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The MIPS proAptiv ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of MIPS proAptiv Fast Processor Model


Model Variant name: proAptiv
Description:
    MIPS32 Configurable Processor Model
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    New proAptiv floating point not implemented yet. Model implements older FP
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    only MIPS32 Instruction set implemented
    MMU Type: Standard TLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Segmentation control implemented
    Enhanced virtual address (EVA) supported
    Vectored interrupts implemented
    MIPS16e ASE implemented
    DSP ASE Rev 2 implemented

Model downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant proAptiv is available OVP_Model_Specific_Information_mips32_r1r5_proAptiv.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32_r1r5/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 12
master DATA 12

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
dint input
int0 input
int1 input
int2 input
int3 input
int4 input
int5 input
int6 input
int7 input
int8 input
int9 input
int10 input
int11 input
int12 input
int13 input
int14 input
int15 input
int16 input
int17 input
int18 input
int19 input
int20 input
int21 input
int22 input
int23 input
int24 input
int25 input
int26 input
int27 input
int28 input
int29 input
int30 input
int31 input
int32 input
int33 input
int34 input
int35 input
int36 input
int37 input
int38 input
int39 input
reset_CPU0 input
hwint0_CPU0 input
hwint1_CPU0 input
hwint2_CPU0 input
hwint3_CPU0 input
hwint4_CPU0 input
hwint5_CPU0 input
nmi_CPU0 input
hwint0 input
vc_run_CPU0 input
reset_CPU1 input
hwint0_CPU1 input
hwint1_CPU1 input
hwint2_CPU1 input
hwint3_CPU1 input
hwint4_CPU1 input
hwint5_CPU1 input
nmi_CPU1 input
vc_run_CPU1 input
reset_CPU2 input
hwint0_CPU2 input
hwint1_CPU2 input
hwint2_CPU2 input
hwint3_CPU2 input
hwint4_CPU2 input
hwint5_CPU2 input
nmi_CPU2 input
vc_run_CPU2 input
reset_CPU3 input
hwint0_CPU3 input
hwint1_CPU3 input
hwint2_CPU3 input
hwint3_CPU3 input
hwint4_CPU3 input
hwint5_CPU3 input
nmi_CPU3 input
vc_run_CPU3 input

No FIFO Ports in proAptiv.


Exceptions


Name Code Description
Int 0
Mod 1
TLBL 2
TLBS 3
AdEL 4
AdES 5
IBE 6
DBE 7
Sys 8
Bp 9
RI 10
CpU 11
Ov 12
Tr 13
FPE 15
Impl1 16
Impl2 17
C2E 18
TLBRI 19
TLBXI 20
MDMX 22
WATCH 23
MCheck 24
Thread 25
DSPDis 26
Prot 29
CacheErr 30

Execution Modes


Mode Code Description
KERNEL 0
DEBUG 1
SUPERVISOR 2
USER 3

More Detailed Information

The proAptiv OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_r1r5_proAptiv.pdf.

Other Sites/Pages with similar information

Information on the proAptiv OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.