Content for OVP Fast Processor Model Variant: MIPS / MIPS64R6

APPLICATION NOTES
(more docs)

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS MIPS64R6


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas MIPS MIPS64R6 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The MIPS MIPS64R6 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of MIPS MIPS64R6 Fast Processor Model


Model Variant name: MIPS64R6
Description:
    MIPS64 Configurable Processor Model
    If you need other variants, these models can be obtained from www.OVPworld.org/MIPSuser.
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    Only MIPS64 Instruction set implemented
    MMU Type: Dual VTLB and FTLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    External interrupt controller implemented
    Vectored interrupts implemented

Model downloadable (needs registration and to be logged in) in package mips64.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant MIPS64R6 is available OVP_Model_Specific_Information_mips64_MIPS64R6.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips64/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 12
master DATA 12

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
dint input
int0 input
int1 input
int2 input
int3 input
int4 input
int5 input
int6 input
int7 input
int8 input
int9 input
int10 input
int11 input
int12 input
int13 input
int14 input
int15 input
int16 input
int17 input
int18 input
int19 input
int20 input
int21 input
int22 input
int23 input
int24 input
int25 input
int26 input
int27 input
int28 input
int29 input
int30 input
int31 input
int32 input
int33 input
int34 input
int35 input
int36 input
int37 input
int38 input
int39 input
int40 input
int41 input
int42 input
int43 input
int44 input
int45 input
int46 input
int47 input
int48 input
int49 input
int50 input
int51 input
int52 input
int53 input
int54 input
int55 input
int56 input
int57 input
int58 input
int59 input
int60 input
int61 input
int62 input
int63 input
int64 input
int65 input
int66 input
int67 input
int68 input
int69 input
int70 input
int71 input
int72 input
int73 input
int74 input
int75 input
int76 input
int77 input
int78 input
int79 input
int80 input
int81 input
int82 input
int83 input
int84 input
int85 input
int86 input
int87 input
int88 input
int89 input
int90 input
int91 input
int92 input
int93 input
int94 input
int95 input
int96 input
int97 input
int98 input
int99 input
int100 input
int101 input
int102 input
int103 input
int104 input
int105 input
int106 input
int107 input
int108 input
int109 input
int110 input
int111 input
int112 input
int113 input
int114 input
int115 input
int116 input
int117 input
int118 input
int119 input
int120 input
int121 input
int122 input
int123 input
int124 input
int125 input
int126 input
int127 input
ej_disable_probe_debug input
ejtagbrk_override input
ej_dint_in input
GCR_CUSTOM_BASE output
GCR_CUSTOM_BASE_UPPER output
dint_CPU0_VP0 input
hwint0_CPU0_VP0 input
hwint1_CPU0_VP0 input
hwint2_CPU0_VP0 input
hwint3_CPU0_VP0 input
hwint4_CPU0_VP0 input
hwint5_CPU0_VP0 input
nmi_CPU0_VP0 input
EICPresent_CPU0_VP0 input
EIC_RIPL_CPU0_VP0 input
EIC_EICSS_CPU0_VP0 input
EIC_VectorNum_CPU0_VP0 input
EIC_VectorOffset_CPU0_VP0 input
EIC_GID_CPU0_VP0 input
intISS_CPU0_VP0 output
causeTI_CPU0_VP0 output
causeIP0_CPU0_VP0 output
causeIP1_CPU0_VP0 output
si_sleep_CPU0_VP0 output
hwint0 input
vc_run_CPU0_VP0 input
Guest.EIC_RIPL_CPU0_VP0 input
Guest.EIC_EICSS_CPU0_VP0 input
Guest.EIC_VectorNum_CPU0_VP0 input
Guest.EIC_VectorOffset_CPU0_VP0 input
Guest.EIC_GID_CPU0_VP0 input
Guest.intISS_CPU0_VP0 output
Guest.causeTI_CPU0_VP0 output
Guest.causeIP0_CPU0_VP0 output
Guest.causeIP1_CPU0_VP0 output
dint_CPU0_VP1 input
hwint0_CPU0_VP1 input
hwint1_CPU0_VP1 input
hwint2_CPU0_VP1 input
hwint3_CPU0_VP1 input
hwint4_CPU0_VP1 input
hwint5_CPU0_VP1 input
nmi_CPU0_VP1 input
EICPresent_CPU0_VP1 input
EIC_RIPL_CPU0_VP1 input
EIC_EICSS_CPU0_VP1 input
EIC_VectorNum_CPU0_VP1 input
EIC_VectorOffset_CPU0_VP1 input
EIC_GID_CPU0_VP1 input
intISS_CPU0_VP1 output
causeTI_CPU0_VP1 output
causeIP0_CPU0_VP1 output
causeIP1_CPU0_VP1 output
si_sleep_CPU0_VP1 output
vc_run_CPU0_VP1 input
Guest.EIC_RIPL_CPU0_VP1 input
Guest.EIC_EICSS_CPU0_VP1 input
Guest.EIC_VectorNum_CPU0_VP1 input
Guest.EIC_VectorOffset_CPU0_VP1 input
Guest.EIC_GID_CPU0_VP1 input
Guest.intISS_CPU0_VP1 output
Guest.causeTI_CPU0_VP1 output
Guest.causeIP0_CPU0_VP1 output
Guest.causeIP1_CPU0_VP1 output
dint_CPU0_VP2 input
hwint0_CPU0_VP2 input
hwint1_CPU0_VP2 input
hwint2_CPU0_VP2 input
hwint3_CPU0_VP2 input
hwint4_CPU0_VP2 input
hwint5_CPU0_VP2 input
nmi_CPU0_VP2 input
EICPresent_CPU0_VP2 input
EIC_RIPL_CPU0_VP2 input
EIC_EICSS_CPU0_VP2 input
EIC_VectorNum_CPU0_VP2 input
EIC_VectorOffset_CPU0_VP2 input
EIC_GID_CPU0_VP2 input
intISS_CPU0_VP2 output
causeTI_CPU0_VP2 output
causeIP0_CPU0_VP2 output
causeIP1_CPU0_VP2 output
si_sleep_CPU0_VP2 output
vc_run_CPU0_VP2 input
Guest.EIC_RIPL_CPU0_VP2 input
Guest.EIC_EICSS_CPU0_VP2 input
Guest.EIC_VectorNum_CPU0_VP2 input
Guest.EIC_VectorOffset_CPU0_VP2 input
Guest.EIC_GID_CPU0_VP2 input
Guest.intISS_CPU0_VP2 output
Guest.causeTI_CPU0_VP2 output
Guest.causeIP0_CPU0_VP2 output
Guest.causeIP1_CPU0_VP2 output
dint_CPU0_VP3 input
hwint0_CPU0_VP3 input
hwint1_CPU0_VP3 input
hwint2_CPU0_VP3 input
hwint3_CPU0_VP3 input
hwint4_CPU0_VP3 input
hwint5_CPU0_VP3 input
nmi_CPU0_VP3 input
EICPresent_CPU0_VP3 input
EIC_RIPL_CPU0_VP3 input
EIC_EICSS_CPU0_VP3 input
EIC_VectorNum_CPU0_VP3 input
EIC_VectorOffset_CPU0_VP3 input
EIC_GID_CPU0_VP3 input
intISS_CPU0_VP3 output
causeTI_CPU0_VP3 output
causeIP0_CPU0_VP3 output
causeIP1_CPU0_VP3 output
si_sleep_CPU0_VP3 output
vc_run_CPU0_VP3 input
Guest.EIC_RIPL_CPU0_VP3 input
Guest.EIC_EICSS_CPU0_VP3 input
Guest.EIC_VectorNum_CPU0_VP3 input
Guest.EIC_VectorOffset_CPU0_VP3 input
Guest.EIC_GID_CPU0_VP3 input
Guest.intISS_CPU0_VP3 output
Guest.causeTI_CPU0_VP3 output
Guest.causeIP0_CPU0_VP3 output
Guest.causeIP1_CPU0_VP3 output
dint_CPU1_VP0 input
hwint0_CPU1_VP0 input
hwint1_CPU1_VP0 input
hwint2_CPU1_VP0 input
hwint3_CPU1_VP0 input
hwint4_CPU1_VP0 input
hwint5_CPU1_VP0 input
nmi_CPU1_VP0 input
EICPresent_CPU1_VP0 input
EIC_RIPL_CPU1_VP0 input
EIC_EICSS_CPU1_VP0 input
EIC_VectorNum_CPU1_VP0 input
EIC_VectorOffset_CPU1_VP0 input
EIC_GID_CPU1_VP0 input
intISS_CPU1_VP0 output
causeTI_CPU1_VP0 output
causeIP0_CPU1_VP0 output
causeIP1_CPU1_VP0 output
si_sleep_CPU1_VP0 output
vc_run_CPU1_VP0 input
Guest.EIC_RIPL_CPU1_VP0 input
Guest.EIC_EICSS_CPU1_VP0 input
Guest.EIC_VectorNum_CPU1_VP0 input
Guest.EIC_VectorOffset_CPU1_VP0 input
Guest.EIC_GID_CPU1_VP0 input
Guest.intISS_CPU1_VP0 output
Guest.causeTI_CPU1_VP0 output
Guest.causeIP0_CPU1_VP0 output
Guest.causeIP1_CPU1_VP0 output
dint_CPU1_VP1 input
hwint0_CPU1_VP1 input
hwint1_CPU1_VP1 input
hwint2_CPU1_VP1 input
hwint3_CPU1_VP1 input
hwint4_CPU1_VP1 input
hwint5_CPU1_VP1 input
nmi_CPU1_VP1 input
EICPresent_CPU1_VP1 input
EIC_RIPL_CPU1_VP1 input
EIC_EICSS_CPU1_VP1 input
EIC_VectorNum_CPU1_VP1 input
EIC_VectorOffset_CPU1_VP1 input
EIC_GID_CPU1_VP1 input
intISS_CPU1_VP1 output
causeTI_CPU1_VP1 output
causeIP0_CPU1_VP1 output
causeIP1_CPU1_VP1 output
si_sleep_CPU1_VP1 output
vc_run_CPU1_VP1 input
Guest.EIC_RIPL_CPU1_VP1 input
Guest.EIC_EICSS_CPU1_VP1 input
Guest.EIC_VectorNum_CPU1_VP1 input
Guest.EIC_VectorOffset_CPU1_VP1 input
Guest.EIC_GID_CPU1_VP1 input
Guest.intISS_CPU1_VP1 output
Guest.causeTI_CPU1_VP1 output
Guest.causeIP0_CPU1_VP1 output
Guest.causeIP1_CPU1_VP1 output
dint_CPU1_VP2 input
hwint0_CPU1_VP2 input
hwint1_CPU1_VP2 input
hwint2_CPU1_VP2 input
hwint3_CPU1_VP2 input
hwint4_CPU1_VP2 input
hwint5_CPU1_VP2 input
nmi_CPU1_VP2 input
EICPresent_CPU1_VP2 input
EIC_RIPL_CPU1_VP2 input
EIC_EICSS_CPU1_VP2 input
EIC_VectorNum_CPU1_VP2 input
EIC_VectorOffset_CPU1_VP2 input
EIC_GID_CPU1_VP2 input
intISS_CPU1_VP2 output
causeTI_CPU1_VP2 output
causeIP0_CPU1_VP2 output
causeIP1_CPU1_VP2 output
si_sleep_CPU1_VP2 output
vc_run_CPU1_VP2 input
Guest.EIC_RIPL_CPU1_VP2 input
Guest.EIC_EICSS_CPU1_VP2 input
Guest.EIC_VectorNum_CPU1_VP2 input
Guest.EIC_VectorOffset_CPU1_VP2 input
Guest.EIC_GID_CPU1_VP2 input
Guest.intISS_CPU1_VP2 output
Guest.causeTI_CPU1_VP2 output
Guest.causeIP0_CPU1_VP2 output
Guest.causeIP1_CPU1_VP2 output
dint_CPU1_VP3 input
hwint0_CPU1_VP3 input
hwint1_CPU1_VP3 input
hwint2_CPU1_VP3 input
hwint3_CPU1_VP3 input
hwint4_CPU1_VP3 input
hwint5_CPU1_VP3 input
nmi_CPU1_VP3 input
EICPresent_CPU1_VP3 input
EIC_RIPL_CPU1_VP3 input
EIC_EICSS_CPU1_VP3 input
EIC_VectorNum_CPU1_VP3 input
EIC_VectorOffset_CPU1_VP3 input
EIC_GID_CPU1_VP3 input
intISS_CPU1_VP3 output
causeTI_CPU1_VP3 output
causeIP0_CPU1_VP3 output
causeIP1_CPU1_VP3 output
si_sleep_CPU1_VP3 output
vc_run_CPU1_VP3 input
Guest.EIC_RIPL_CPU1_VP3 input
Guest.EIC_EICSS_CPU1_VP3 input
Guest.EIC_VectorNum_CPU1_VP3 input
Guest.EIC_VectorOffset_CPU1_VP3 input
Guest.EIC_GID_CPU1_VP3 input
Guest.intISS_CPU1_VP3 output
Guest.causeTI_CPU1_VP3 output
Guest.causeIP0_CPU1_VP3 output
Guest.causeIP1_CPU1_VP3 output

No FIFO Ports in MIPS64R6.


Exceptions


Name Code Description
Int 0
Mod 1
TLBL 2
TLBS 3
AdEL 4
AdES 5
IBE 6
DBE 7
Sys 8
Bp 9
RI 10
CpU 11
Ov 12
Tr 13
MSAFPE 14
FPE 15
Impl1 16
Impl2 17
C2E 18
TLBRI 19
TLBXI 20
MSADis 21
MDMX 22
WATCH 23
MCheck 24
Thread 25
DSPDis 26
GE 27
Prot 29
CacheErr 30

Execution Modes


Mode Code Description
KERNEL 0
DEBUG 1
SUPERVISOR 2
USER 3
GUEST_KERNEL 4
GUEST_SUPERVISOR 5
GUEST_USER 6

More Detailed Information

The MIPS64R6 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips64_MIPS64R6.pdf.

Other Sites/Pages with similar information

Information on the MIPS64R6 OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.