Content for OVP Fast Processor Model Variant: Renesas / RL78-S1

APPLICATION NOTES
(more docs)

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Renesas RL78-S1


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas Renesas RL78-S1 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The Renesas RL78-S1 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of Renesas RL78-S1 Fast Processor Model


Model Variant name: RL78-S1
Description:
    RL78 Family Processor Model.
Licensing:
    Open Source Apache 2.0
Reference:
    RL78 User Manual: Software, Single-Chip microcontrollers, http://documentation.renesas.com/doc/products/mpumcu/doc/rl78/r01us0015e...
Limitations:
    All instructions are supported except the MULU, MULHU, MULH, DIVHU, MACHU and MACH instructions that are not implemented.
    Banked registers are not supported
    The PMC (Processor Model Control) register behavior is not modeled.
    This processor model requires that RAM is available at the address range of the memory mapped registers
    Address ranges 0xFFEE0 to 0xFFEFF for General purpose registers (e.g. X, A)
    Address ranges 0xFFFF0 to 0xFFFFF for special function registers (e.g. SP)
    This processor model should be started with a reset signal. The processor reads from the reset vector 0x0000 on reset and uses this value for the initial PC
Verification:
    Models have been tested by eSOL TRINITY and Imperas
Features:
    External exceptions are supported
    The BRK instruction (internal trap) is supported
    Memory mirroring is supported
    Memory mapped registers is supported

Model downloadable (needs registration and to be logged in) in package rl78.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant RL78-S1 is available OVP_Model_Specific_Information_rl78_RL78-S1.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: renesas.ovpworld.org/processor/rl78/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0xc5
QuantumLeap Support: The processor model has not yet been qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 20
master DATA 20
slave GPRSP 0
slave SFRSP 0

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
extint input
intAck output

No FIFO Ports in RL78-S1.


Exceptions


Name Code Description
RST 0
TRP 0
IAW 0
BRK 126
IRQ 65535

Execution Modes


Mode Code Description
RB0 0
RB1 1
RB2 2
RB3 3

More Detailed Information

The RL78-S1 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_rl78_RL78-S1.pdf.

Other Sites/Pages with similar information

Information on the RL78-S1 OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.