Content for OVP Fast Processor Model Variant: RISC-V / RV32GCV

DOWNLOAD REFERENCE/DEMO PLATFORMS

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for RISC-V RV32GCV


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas RISC-V RV32GCV ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The RISC-V RV32GCV ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of RISC-V RV32GCV Fast Processor Model


Model Variant name: RV32GCV
Description:
    RISC-V RV32GCV 32-bit processor model
Licensing:
    This Model is released under the Open Source Apache 2.0
Extensions:
    The model has the following architectural extensions enabled, and the following bits in the misa CSR Extensions field will be set upon reset:
    misa bit 0: extension A (atomic instructions)
    misa bit 2: extension C (compressed instructions)
    misa bit 3: extension D (double-precision floating point)
    misa bit 5: extension F (single-precision floating point)
    misa bit 8: RV32I/64I/128I base ISA
    misa bit 12: extension M (integer multiply/divide instructions)
    misa bit 18: extension S (Supervisor mode)
    misa bit 20: extension U (User mode)
    misa bit 21: extension V (vector instructions)
    To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register.
    Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any value defined in the base variant.
    Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
    Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any value defined in the base variant.
Available (But Not Enabled) Extensions:
    The following extensions are supported by the model, but not enabled by default in this variant:
    misa bit 4: RV32E base ISA (NOT ENABLED)
    misa bit 13: extension N (user-level interrupts) (NOT ENABLED)
    misa bit 23: extension X (non-standard extensions present) (NOT ENABLED)
    To add features from this list to the base variant, use parameter "add_Extensions". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are absent.
Features:
    On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
    Values written to "mtvec" are masked using the value 0xfffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
    The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
    Values written to "stvec" are masked using the value 0xfffffffd. A different mask of writable bits may be specified using parameter "stvec_mask" if required. parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment in the same manner as for the "mtvec" register, described above.
    On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
    On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
    WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
    The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
    The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
    The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
    A 9-bit ASID is implemented. Use parameter "ASID_bits" to specify a different implemented ASID size if required.
    This variant supports address translation modes 0 and 1. Use parameter "Sv_modes" to specify a bit mask of different modes if required.
    Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
    Unaligned memory accesses are not supported for AMO instructions by this variant. Set parameter "unalignedAMO" to "T" to enable such accesses.
    16 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit. The PMP grain size (G) is 0, meaning that PMP regions as small as 4 bytes are implemented. Use parameter "PMP_grain" to specify a different grain size if required.
    LR/SC instructions are implemented with a 1-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".
    By default, the processor starts with floating-point instructions disabled (mstatus.FS=0). Use parameter "mstatus_FS" to force mstatus.FS to a non-zero value for floating-point to be enabled from the start.
    The D extension is enabled in this variant independently of the F extension. Set parameter "d_requires_f"to "T" to specify that the D extension requires the F extension to be enabled.
    This variant implements floating point status in mstatus.FS as defined in the Privileged Architecture specification. To specify that a simpler mode supporting only values 0 (Off) and 3 (Dirty) should be used, Set parameter "fs_always_dirty" to "T". When this simpler mode is used, any write of values 1 (Initial) or 2 (Clean) from privileged code behave as if value 3 was written.
Vector Extension:
    This variant implements the RISC-V base vector extension with version specified in the References section of this document.
Vector Extension Parameters:
    Parameter ELEN is used to specify the maximum size of a single vector element in bits (32 or 64). By default, ELEN is set to 64 in this variant.
    Parameter VLEN is used to specify the number of bits in a vector register (a power of two in the range 32 to 2048). By default, VLEN is set to 512 in this variant.
    Parameter SLEN is used to specify the striping distance (a power of two in the range 32 to 2048). By default, SLEN is set to 64 in this variant.
    Parameter Zvlsseg is used to specify whether the Zvlsseg extension is implemented. By default, Zvlsseg is set to 1 in this variant.
    Parameter Zvamo is used to specify whether the Zvamo extension is implemented. By default, Zvamo is set to 1 in this variant.
    Parameter Zvediv will be used to specify whether the Zvediv extension is implemented. This is not currently supported.
Vector Extension Features:
    The model implements the base vector extension with a maximum ELEN of 64. Striping, masking and polymorphism are all fully supported. Zvlsseg and Zvamo extensions are fully supported. The Zvediv extension specification is subject to change and therefore not yet supported.
    Single precision and double precision floating point types are supported if those types are also supported in the base architecture (i.e. the corresponding D and F features must be present and enabled). Presently, the interaction of vector floating point with the Privileged Architecture is not well defined; this model assumes that vector floating point operations may only be executed if the base floating point unit is also enabled (i.e. mstatus.FS must be non-zero). Attempting to execute vector floating point instructions when mstatus.FS is 0 will cause an Illegal Instruction exception.
    The model assumes that all vector memory operations must be aligned to the memory element size. Unaligned accesses will cause a Load/Store Address Alignment exception.
Interrupts:
    The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
    The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
    All other interrupt ports are active high.
Debug Mask:
    It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
    Value 0x002: enable debugging of PMP and virtual memory state;
    Value 0x004: enable debugging of interrupt state.
    All other bits in the debug bitmask are reserved and must not be set to non-zero values.
Integration Support:
    This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
CSR Register External Implementation:
    If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.
LR/SC Active Address:
    Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    The processor fully supports the architecturally-specified floating-point instructions.
    Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.
    The TLB is architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.
Verification:
    All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
References:
    The Model details are based upon the following specifications:
    RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20190305-Base-Ratification)
    RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 20190405-Priv-MSU-Ratification)
    RISC-V "V" Vector Extension (Vector Architecture Version 0.7.1-draft-20190605)

Model downloadable (needs registration and to be logged in) in package riscv.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant RV32GCV is available OVP_Model_Specific_Information_riscv_RV32GCV.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: riscv.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 32
master DATA 32

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
nmi input
SSWInterrupt input
MSWInterrupt input
STimerInterrupt input
MTimerInterrupt input
SExternalInterrupt input
MExternalInterrupt input

No FIFO Ports in RV32GCV.


Exceptions


Name Code Description
InstructionAddressMisaligned 0
InstructionAccessFault 1
IllegalInstruction 2
Breakpoint 3
LoadAddressMisaligned 4
LoadAccessFault 5
StoreAMOAddressMisaligned 6
StoreAMOAccessFault 7
EnvironmentCallFromUMode 8
EnvironmentCallFromSMode 9
EnvironmentCallFromMMode 11
InstructionPageFault 12
LoadPageFault 13
StoreAMOPageFault 15
SSWInterrupt 65
MSWInterrupt 67
STimerInterrupt 69
MTimerInterrupt 71
SExternalInterrupt 73
MExternalInterrupt 75

Execution Modes


Mode Code Description
User 0
Supervisor 1
Machine 3

More Detailed Information

The RV32GCV OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_riscv_RV32GCV.pdf.

Other Sites/Pages with similar information

Information on the RV32GCV OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.