Content for OVP Fast Processor Model Variant: SiFive / E51

APPLICATION NOTES
(more docs)
DOWNLOAD REFERENCE/DEMO PLATFORMS

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for SiFive E51


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas SiFive E51 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The SiFive E51 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of SiFive E51 Fast Processor Model


Model Variant name: E51
Description:
    RISC-V E51 64-bit processor model
Licensing:
    This Model is released under the Open Source Apache 2.0
Features:
    The model supports the following architectural features, defined in the misa CSR:
    extension A (atomic instructions)
    extension C (compressed instructions)
    RV32I/64I/128I base ISA
    extension M (integer multiply/divide instructions)
    extension U (User mode)
    64-bit XLEN
    If required, supported architectural features may be overridden using parameter "misa_Extensions". Parameter "misa_Extensions_mask" can be used to specify which features can be dynamically enabled or disabled by writes to the misa register.
    On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
    Values written to "mtvec" are masked using the value 0x3ffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 64.
    The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
    On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
    On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
    WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
    The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
    The "time" CSR is not implemented in this variant and reads of it will require emulation in Machine mode. Set parameter "time_undefined" to False to instead specify that "time" is implemented.
    The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
    Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
    8 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit.
    LR/SC instructions are implemented with a 64-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".
Interrupts:
    The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
    The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
    All other interrupt ports are active high.
Debug Mask:
    It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
    Value 0x002: enable debugging of PMP and virtual memory state;
    Value 0x004: enable debugging of interrupt state.
    All other bits in the debug bitmask are reserved and must not be set to non-zero values.
Integration Support:
    This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
CSR Register External Implementation:
    If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.
LR/SC Active Address:
    Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.
Verification:
    All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
References:
    The Model details are based upon the following specifications:
    ---- RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.3-draft)
    ---- RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.11-draft)
    ---- SiFive E51 Core Complex Manual v1p2

Model downloadable (needs registration and to be logged in) in package sifive_riscv.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant E51 is available OVP_Model_Specific_Information_sifive_riscv_E51.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: sifive.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 32
master DATA 32

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
nmi input
MSWInterrupt input
MTimerInterrupt input
MExternalInterrupt input
LocalInterrupt0 input
LocalInterrupt1 input
LocalInterrupt2 input
LocalInterrupt3 input
LocalInterrupt4 input
LocalInterrupt5 input
LocalInterrupt6 input
LocalInterrupt7 input
LocalInterrupt8 input
LocalInterrupt9 input
LocalInterrupt10 input
LocalInterrupt11 input
LocalInterrupt12 input
LocalInterrupt13 input
LocalInterrupt14 input
LocalInterrupt15 input

No FIFO Ports in E51.


Exceptions


Name Code Description
InstructionAddressMisaligned 0
InstructionAccessFault 1
IllegalInstruction 2
Breakpoint 3
LoadAddressMisaligned 4
LoadAccessFault 5
StoreAMOAddressMisaligned 6
StoreAMOAccessFault 7
EnvironmentCallFromUMode 8
EnvironmentCallFromMMode 11
InstructionPageFault 12
LoadPageFault 13
StoreAMOPageFault 15
MSWInterrupt 67
MTimerInterrupt 71
MExternalInterrupt 75
LocalInterrupt0 80
LocalInterrupt1 81
LocalInterrupt2 82
LocalInterrupt3 83
LocalInterrupt4 84
LocalInterrupt5 85
LocalInterrupt6 86
LocalInterrupt7 87
LocalInterrupt8 88
LocalInterrupt9 89
LocalInterrupt10 90
LocalInterrupt11 91
LocalInterrupt12 92
LocalInterrupt13 93
LocalInterrupt14 94
LocalInterrupt15 95

Execution Modes


Mode Code Description
User 0
Machine 3

More Detailed Information

The E51 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_sifive_riscv_E51.pdf.

Other Sites/Pages with similar information

Information on the E51 OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.