Content for OVP Fast Processor Model Variant: Xilinx MicroBlaze / V7_10

APPLICATION NOTES
(more docs)

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Xilinx MicroBlaze V7_10


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas Xilinx MicroBlaze V7_10 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The Xilinx MicroBlaze V7_10 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of Xilinx MicroBlaze V7_10 Fast Processor Model


Model Variant name: V7_10
Description:
    Microblaze Processor Model
Licensing:
    Apache 2.0 Open Source License
Features:
    Instruction Set: This model fully implements the instruction set upto and including V10.
    Privileged Instructions: Implemented
    Virtual-Memory Management: Implemented
    Reset, Interrupts, Exceptions and Break: Implemented
    Floating Point Unit: Implemented
    Stream Link Interface: Implemented
Limitations:
    GDB: There is a known issue in the microblaze gdb, a lockup can occur when disassembling from address 0
ConfigurationFeatures:
    Barrel Shifter.
    Hardware Divider.
    Machine Status Set/Clear Instructions.
    Hardware Exceptions.
    Pattern Compare Instructions.
    Floating Point Unit (FPU).
    Disable Hardware Multiplier.
    Processor Version Register (PVR).
    Hardware Multiplier 64-bit Result.
    Floating Point Conversion and Square Root Instructions.
    Memory Management Unit.
    Extended Stream Instructions .
Verification:
    Models have been validated correct by running through extensive tests using test suites and technology provided by Xilinx

Model downloadable (needs registration and to be logged in) in package microblaze.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant V7_10 is available OVP_Model_Specific_Information_microblaze_V7_10.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: xilinx.ovpworld.org/processor/microblaze/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xbd
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 32
master DATA 32

SystemC Signal Ports (Net Ports)


Port Type Name Description
Interrupt input
Reset input
MB_Reset input
Ext_BRK input
Ext_NM_BRK input

No FIFO Ports in V7_10.


Exceptions


Name Code Description
STREAM_EXCEPTION 0
UNALIGNED_DATA_ACCESS 1
ILLEGAL_OPCODE_EXCEPTION 2
INSTRUCTION_BUS_ERROR_EXCEPTION 3
DATA_BUS_ERROR_EXCEPTION 4
DIVIDE_EXCEPTION 5
FLOATING_POINT_UNIT_EXCEPTION 6
PRIVILEGED_INSTRUCTION_EXCEPTION 7
STACK_PROTECTION_VIOLATION_EXCEPTION 8
DATA_STORAGE_EXCEPTION 9
INSTRUCTION_STORAGE_EXCEPTION 10
DATA_TLB_MISS_EXCEPTION 11
INSTRUCTION_TLB_MISS_EXCEPTION 12
RESET 13
INTERRUPT 14

Execution Modes


Mode Code Description
REAL 0
VIRTUAL_PRIV 1
VIRTUAL_USER 2

More Detailed Information

The V7_10 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_microblaze_V7_10.pdf.

Other Sites/Pages with similar information

Information on the V7_10 OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.