When OVP was being created, there was much talk of how TLM2 enables SystemC to become the glue for putting platforms together using models written in C, C++, or SystemC. Many people interested in the high speed models of OVP, especially the certified processor models, requested that we see if OVP models could work efficiently within a SystemC TLM environment.
In OVP, models have bus interfaces that are transaction oriented. We spent time reviewing the TLM2 specification so we could understand how to make OVP fast models best work in this TLM infrastructure.
We completed that work and all OVP processor models come with a TLM2 interface layers (wrappers) enabling them to be used natively in SystemC TLM2 platforms. OVP peripherals can also have a wrapper layer to enable their use in SystemC TLM2 platforms. We also provide the peripheral models in the library with these SystemC TLM2 interfaces as part of the standard OVP release.
We create these interfaces using the iGen tool which is a standard part of the OVP download package. iGen is used to assist in the creation of the C code of the models, and also iGen creates the native SystemC TLM2 interface for all the models.
We are very pleased with the result and now any SystemC TLM2 user can access OVP processor models of ARM, MIPS, ARC, Renesas, PowerPC, Altera, Xilinx, and OR1K processors running 500-1,000 MIPS. They can also use any of the 200 peripheral components in the library including fully functional ethernet and USB components.
The fastest recorded speed on a 3.5GHz desktop PC is a simulation of a MIPS 32 bit RISC running the peakspeed2 benchmark at 7,427 MIPS (yes over 7 Billion Instructions Per Second!).
Thank you to the many companies and individuals from the following entities that agreed to review our beta code and to those that provided valuable feedback:
Analog Devices, Cadence, Doulos, Elda, EVE, Forte, GreenSocs, HCL Technologies, IIT Delhi, Imperas, Intel, Posedge Software, University of Lugano.
OSCI TLM2 is a layer for interoperability between memory mapped bus models. There is a generic payload with extension mechanism, an API for memory mapped bus modeling, and there can be loosely-timed and aproximately-timed modeling.
Loosely-timed is the higher performance of the two timing models and enables processes to run ahead of simulation time (temporal decoupling) and uses a "quantum keeper". Transactions can use a blocking transport interface and can include timing annotation.
There is also a Direct Memory Interface (DMI). This gives the initiator a direct pointer to memory in the target and bypasses the sockets in normal transport calls. There are extensions for security modes and the target can invalidate the DMI pointer if needed.
The goal of the TLM2 OVP integration is to provide OVP CPU models that work in SystemC platforms as fast as possible.
Our approach is to provide native interfaces (wrappers) of all OVP CPUs and all OVP peripherals.
The OVP solution allows memory to be instantiated in the OVP subsystem or outside the OVP subsystem as SystemC memory. The TLM2 DMI capability can be used, and OVP CPU models initiate a DMI negotiation by default.
The use of memory in the OVP models is required for efficient SMP, CMP, shared memory, and, sparse memory systems - please read more in the OVP documentation regarding this.
For convenience we have also provided variants of a TLM2 bus decoder and memory model.
If you go to the OVPworld download page, you can see there are many examples and demonstrations of platforms that are written in SystemC TLM2. These range from simple bare metal platforms to full blown Extendable Platform Kits that instance multiple processor and boot SMP linux.
As part of the OVP main download package there is a program iGen. iGen is a model building wizard that takes a concise tcl input script that makes calls to powerful functions and iGen outputs C code of the structure of the models, but also can write out SystemC TLM2.
For platforms, iGen can create complete SystemC TLM2 platforms.
For models, iGen creates the C templates including stubs for user extension of behavior. For models, iGen also creates full SystemC TLM2 interfaces enabling the models to be used in SystemC TLM2 platforms.
There is a generic interface (wrapper) that is put around all OVP CPU models. This wrapper is used in a processor configuration specific layer which is then instanced into the SystemC platform. The wrappers do not have separate data and instruction buses - this could be added. The wrappers do support interrupts and allow control of all model features using configuration attributes.
The CPU models automatically use DMI by default - meaning that they negotiate the best possible performance with the memory subsystem.
Behavioral and Peripheral models can be bus master or slave and work with interrupts. Automatic DMI has not been implemented in the behavioral model wrappers (if you need this in your bus mastering peripheral please contact us for examples).
There is a global quantum implemented and time is synchronized between OVP cpu models, peripheral models and SystemC time.
With the TLM2 interfaces we have not implemented the standard OVP features of dynamic bus mapping and memory invalidate.
OVP is providing a rich set of open source processor models, that currently include ARC, ARM, MIPS, RENESAS, Xilinx, Altera, PowerPC and OR1K processor families. These are fast, free, and easy to use.
TLM2 can be used as glue to stick models together to create virtual platforms using SystemC.
With the OVP TLM2 support, it is easy to use OVP model within TLM2 platforms to gain performance.
Please visit the download TLM2 section of the downloads page to download the models and interfaces so that you can use them with your SystemC platforms.
If you want to read the user guide that explains how OVP models are used within TLM2 platforms, read the OVPsim_Using_OVP_Models_in_SystemC_TLM2.0_Platforms.pdf document.
Please download the OVPsim and other packages and look in the Examples and Demo directories for some self contained SystemC TLM2 platforms that show the source of how to use these OVP models in your TLM2 platforms.
Also, please look in the OVPsim packages Demo directories for some self contained demonstrations of the OVP TLM2 integration running different benchmark simulations.
If you require further information, please have a look at the forums and post a question, or email us.