Models on this OVP website are those recently developed by Imperas and provided to OVP. These models are provided as ready to run object and also as source. The source of the models is provided in the packages downloaded from this site.
The models on the OVP site download packages will be those that have been validated by OVP and verified against a verification suite. Users can also upload their own packages onto the OVPworld library pages.
It is very easy to develop your own models - the APIs and OVPsim simulator are all you need. If you are doing a processor model, a good starting place is to look at the source of the OR1K model or the MIPS model and to see the VMI training material based around it.
If you develop your own models and would like them to become hosted here on OVP then please contact us at info[at]ovpworld.org. We will need to be provided the source and the verification suites. When quality is sufficient they will be hosted here. You can also create your own page on the library wiki.
If you need a model that we do not have here - please request them in the forums.
If you need a model developed, then please contact us here, or contact one of the model building organizations such as Imperas at info[at]Imperas.com.
Below you will find specific information as to which models are currently available and those under development.
If you are planning building your own models - contact us for advice, assistance etc.
Are the models free you may ask - and yes the models from OVP are free - even the vendor verified advanced multicore processor models. There will be other providers of models in due course and they may charge for models.
At Imperas all OVP models are developed, compiled and validated against MinGW/MSYS on X86 PC running Windows and also using Linux on x86 PCs.
For users running Windows operating systems, OVP recommends using MinGW and MSYS from www.mingw.org.
The models on the OVP site are available in current version only from the main pages. There is also a previous releases page where many model packages are available from previous releases.
The OVPsim simulator executes the different models. VMI processor models are run as Just-In-Time Code Morphing Instruction Accurate models whereas peripheral models using BHM/PPM are simulated in the simulator on a Peripheral Simulation Engine (PSE) in a safe environment.
Models are typically provided as dynamically linked libraries. Platforms can be shipped as executables or dynamically linked libraries.
Currently there are many example platforms - from 1 to 24 processors. Several real platforms are currently under development, for example there is a MIPS Malta platform that boots Linux and Android, and several ARM platforms including the Versatile Express platform that can boot SMP Linux on ARM Cortex-A9MP - please check the library tab and forum for latest details.
Several processor models have been developed using the OVP methodology and APIs. On this site there are currently several model families - OpenCores, ARM, Synopsys ARC, MIPS, PowerPC, Xilinx, Renesas,... There have been other models developed using OVP technology but these remain proprietary to their developers / users.
It is normal practise for each processor model to be listed on the OVP site with several examples / benchmarks enabling the verification that it is installed and running correctly.
Currently available is the OR1K model.
Core model, and does not have MMU/TLB.
The latest suite of ARM models are based on the ARMv4, ARMv5, ARMv6, ARMv7 ISA and the models can be used with selectable ISA capabilities including
ARMv4xM ARMv4 ARMv4TxM ARMv4T
ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ
ARMv6 ARMv6K ARMv6T2
ARMv7 ARMv7-A ARMv7-M
The models are available preconfigured and include:
ARM7TDMI, ARM720T, ARM7EJ-S,
ARM920T, ARM922T, ARM926EJ-S, ARM940T, ARM946E, ARM966E-S ARM968E-S
ARM1020E, ARM1022E, ARM1026EJ-S
ARM Cortex-A9MP, ARM Cortex-A9MPx1, ARM Cortex-A9MPx2, ARM Cortex-A9MPx3, ARM Cortex-A9MPx4
ARM Cortex-M3, ARM Cortex-M4, ARM Cortex-M4F
MMU, MPU, TCM, VFP, NEON, Jazelle, TrustZone are fully implemented.
Also available for free download are Virtual Platforms for simulating full platforms.
For the ARM there are the ARM IntegratorCP and ARM Versatile Express platforms that runs Linux Kernel 2.6 and Mentors Nucleus operating systems. There is also the Atmel AT91SAM7 virtual platform that can run with the uClinux operating system. These platforms come with all peripherals and for the Linux platforms include the OS binaries so you can just download and boot.
Currently available are the Synopsys ARC 600 and ARC 700 families including the ARC605. The models have been verified correct by Virage Logic (Acquired by Synopsys).
Currently available are the Renesas v850 family (acquired with NEC Electronics Ltd). This includes the v850, v850es, v850e1, and v850e2 processor variants.
In the May 2010 release, OVP included the first version of a PowerPC processor model. It is Core Instruction Set Architecture only. The Instruction set implemented for the current version of this model is based upon the Freescale MPCxxx Instruction set. These instructions are documented in the Freescale document MPC82XINSET.pdf.
Currently available and verified by MIPS Technologies are:
MIPS32 ISA model.
Specific core models:
MIPS 4Km, 4Kc, 4Kp.
MIPS 4KEm, 4KEc, 4KEp.
MIPS 24KEc, 24KEf, 24Kc, and 24Kf.
MIPS 34Kc, 34Kf. (Dualcore)
MIPS 74Kc and 74Kf.
MIPS1004Kc, MIPS1004Kf. (Quadcore)
M14K, M14Kc. (microMIPS compressed instruction set)
MIPS32 1074Kc, 1074Kf. (Quadcore)
MIPS32 proAptiv. (1-6 cores)
MIPS32 interAptiv. (1-4 cores)
All MIPS models can be configured as big or little endian.
Development at Southampton University, UK - is available as open source. Models open SPARC V8. Available from Library pages.
Currently under development.
Models of the Xilinx MicroBlaze processor being developed and verified:
V7_10, V7_20, V7_30
V8_10, V7_20, V9_30
Currently available is a wrapper that enables the Tensilica provided models of the Xtensa and Diamond Standard cores to be used as if they were OVP native processor models.
Within the OVP distribution is a simple library of basic behavioral peripherals like UART, Timer, DMA, etc. There are also all the peripherals needed to boot Linux. There is currently ongoing work to complete the basic PC set of peripherals. Please check the forum for more information.
It is easy to write peripheral models - the simplest being register state and a few callbacks. There are two APIs needed - BHM, PPM.