Technology OVP Models

General Information about OVP Models

Models on this OVP website are those recently developed by Imperas and provided to OVP. These models are provided as ready to run object and also as source. The source of the models is provided in the libary wiki and also from Google Code.

When the models are on open source repositories like Google Code and others companies create new models etc, the models on the OVP site will be those that have been validated by OVP and verified against a verification suite.

It is very easy to develop your own models - the APIs and OVPsim simulator are all you need. If you are doing a processor model, a good starting place is to look at the source of the OR1K model or the MIPS model and to see the VMI training material based around it.

If you develop your own models and would like them to become hosted here on OVP then please contact us at info[at]ovpworld.org. We will need to be provided the source and the verification suites. When quality is sufficient they will be hosted here. You can also create your own page on the library wiki.

If you need a model that we do not have here - please request them in the forums.

If you need a model developed, then please contact us here, or contact one of the model building organizations such as Imperas at info[at]Imperas.com.

Below you will find specific information as to which models are currently available and those under development.

If you are planning building your own models - contact us for advice, assistance etc.

Are the models free you may ask - and yes the models from OVP are free - even the vendor verified advanced multicore processor models. There will be other providers of models in due course and they may charge for models.

At Imperas and OVP all models are developed, compiled and validated against MinGW and MSYS on X86 PC running Windows Professional SP2.

For users running Windows operating systems, OVP recommends using MinGW and MSYS from www.mingw.org. Current versions are gcc version 3.4.5 and MinGW runtime version 3.14 for Windows.

The models on the OVP site are only available in current version only.

The OVPsim simulator executes the different models. VMI processor models are run as Just-In-Time Code Morphing Instruction Accurate models whereas peripheral models using BHM/PPM are simulated in the simulator on a Peripheral Simulation Engine (PSE) in a safe environment.

Models are typically provided as dynamically linked libraries. Platforms can be shipped as executables or dynamically linked libraries.

Platform Models

Currently there are many example platforms - from 1 to 24 processors. Several real platforms are currently under development, for example there is a MIPS Malta platform that boots Linux - please check the library tab and forum for latest details.

Processor Models

Several processor models have been developed using the OVP methodology and APIs. On this site there are currently several model families - OpenCore OR1K, ARM, ARC, and MIPS. There have been other models developed using OVP technology but these remain proprietary to their developers / users.

It is normal practise for each processor model to be listed on the OVP site with several examples / benchmarks enabling the verification that it is installed and running correctly.

OpenCore OpenRISC Models

Currently available is the OR1K model.

Core model, and does not have MMU/TLB.

ARM Models

The latest suite of ARM models are based on the ARMv4 and ARMv5 ISA and the models can be used with selectable ISA capabilities including
ARMv4xM ARMv4 ARMv4TxM ARMv4T
ARMv5xM ARMv5 ARMv5TxM ARMv5T ARMv5TExP ARMv5TE ARMv5TEJ.

The models are available preconfigured and include:
ARM7TDMI, ARM720T, ARM7EJ-S,
ARM920T, ARM922T, ARM926EJ-S, ARM940T, ARM946E, ARM966E-S ARM968E-S
ARM1020E, ARM1022E, ARM1026EJ-S

MMU, MPU, and TCM are implemented.

Also available for free download are Virtual Platforms for simulating full platforms.
For the ARM there is the ARM IntegratorCP platform that runs Linux Kernel 2.6 and Mentor's Nucleus operating systems. There is also the Atmel AT91SAM7 virtual platform that can run with the uClinux operating system. These platforms come with all peripherals and for the Linux platforms include the OS binaries so you can just download and boot.

Virage ARC Models

Currently available are the Virage ARC 600 and ARC 700 families including the ARC605. The models have been verified correct by Virage Logic.

NEC Models

Currently available are the NEC Electronics Ltd v850 family. This includes the v850, v850es, v850e1, and v850e2 processor variants.

Power Architecture Models

In the May 2010 release, OVP included the first version of a PowerPC processor model. It is Core Instruction Set Architecture only. The Instruction set implemented for the current version of this model is based upon the Freescale MPCxxx Instruction set. These instructions are documented in the Freescale document MPC82XINSET.pdf.

MIPS Models

Currently available and verified by MIPS Technologies are:
MIPS32 ISA model.
Specific core models:
MIPS4KEm.
MIPS4KEc including MMU/TLB.
MIPS4KEp.
MIPS24KEc, 24KEf, 24Kc, and 24Kf.
The multicore (dualcore): MIPS 34Kc, 34Kf.
MIPS74Kc and MIPS74Kf.
The multicore (quad core) MIPS1004Kc, MIPS1004Kf.
The new microMIPS compressed instruction set and M14K, M14Kc.
All MIPS models can be configured as big or little endian.

openSPARC Models

Development at Southampton University, UK - is available as open source. Models open SPARC V8. Available from Library pages.

Tensilica Models

Currently available is a wrapper that enables the Tensilica provided models of the Xtensa and Diamond Standard cores to be used as if they were OVP native processor models.
Please see the www.ovpworld.org/library page for more specific information.

Peripherals Models

Within the OVP distribution is a simple library of basic behavioral peripherals like UART, Timer, DMA, etc. There are also all the peripherals needed to boot Linux. There is currently ongoing work to complete the basic PC set of peripherals. Please check the forum for more information.

It is easy to write peripheral models - the simplest being register state and a few callbacks. There are two APIs needed - BHM, PPM.