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Open Virtual Platforms Forum Index
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  Topic: Error (RISCV/PK) SYSCALL(unhandled(*))
DuncGrah

Replies: 10
Views: 594

PostForum: Ask a Question   Posted: Fri Apr 08, 2022 12:42 am   Subject: Error (RISCV/PK) SYSCALL(unhandled(*))
There are often issues with RISC-V toolchains and versions of the extensions they support.
For ease of use, Imperas have provided some precompiled GCC versions on their public GitHub: https://github. ...
  Topic: ETH / TCP communication
DuncGrah

Replies: 1
Views: 388

PostForum: Host Platforms   Posted: Mon Feb 28, 2022 2:42 am   Subject: ETH / TCP communication
First point to note is that the interface supports TCP/IP traffic and ping uses ICMP which is not supported so you cannot use ping to determine if the interface is alive.

The Ethernet interface mod ...
  Topic: On the time slice induced accuracy
DuncGrah

Replies: 1
Views: 454

PostForum: About Open Virtual Platforms and its EcoSystem   Posted: Thu Feb 03, 2022 5:39 am   Subject: On the time slice induced accuracy
for (1) I think you are correct. The time slice must be smaller than the minimum delay required. I think this requires a minor documentation change.

for (2) I cannot think of an obvious reason that ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 1138

PostForum: Ask a Question   Posted: Thu Nov 18, 2021 1:03 am   Subject: how can monitoring at run-time the instructions executed
There are OP API functions that allow you to monitor accesses.
You will get the data of the transaction provided in the callback, so the instruction binary on an instruction fetch. Please review the ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 1138

PostForum: Ask a Question   Posted: Wed Nov 17, 2021 6:45 am   Subject: how can monitoring at run-time the instructions executed
I am afraid there is no function available in the OP or VMI APIs that allow an instruction to be decoded. The instruction decode information is all embeded in the processor models.
There are function ...
  Topic: how can monitoring at run-time the instructions executed
DuncGrah

Replies: 5
Views: 1138

PostForum: Ask a Question   Posted: Tue Nov 16, 2021 2:05 am   Subject: how can monitoring at run-time the instructions executed
You can add callbacks onto the bus or memory that can be used to detect accesses and determine the data. Please see the monitoring functions in the OP API.
  Topic: bhmWaitDelay in instruction fetch memory access
DuncGrah

Replies: 2
Views: 2115

PostForum: Ask a Question   Posted: Fri Oct 29, 2021 12:56 am   Subject: bhmWaitDelay in instruction fetch memory access
I have re-created this issue. We have decided that this is using the peripheral model delays in a way in which they were not intended. Because the instruction is re-started after the delay the simple ...
  Topic: SystemC model and OVP environment
DuncGrah

Replies: 4
Views: 3060

PostForum: Getting started   Posted: Thu Oct 28, 2021 1:45 am   Subject: SystemC model and OVP environment
Universities can register for the Imperas University Program. This can provide access to the professional products free of charge for academic and educational usage.
Please contact univ@imperas.com
  Topic: bhmWaitDelay in instruction fetch memory access
DuncGrah

Replies: 2
Views: 2115

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 11:55 pm   Subject: bhmWaitDelay in instruction fetch memory access
What you are doing looks correct, we will try to figure out what you are seeing and why it is happening .. will get back to you asap :)
  Topic: Is there a true random number generator?
DuncGrah

Replies: 2
Views: 2874

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 8:36 am   Subject: Is there a true random number generator?
I don't believe that there is such a thing in a processor.
  Topic: Segmentation fault with Examples/PlatformConstruction/System
DuncGrah

Replies: 1
Views: 1409

PostForum: Ask a Question   Posted: Wed Oct 27, 2021 8:35 am   Subject: Segmentation fault with Examples/PlatformConstruction/System
It is very important that "everything" is rebuilt using the same C++ compiler and flags.
The build process has been improved in the forthcoming next release but at the moment can you try se ...
  Topic: SystemC model and OVP environment
DuncGrah

Replies: 4
Views: 3060

PostForum: Getting started   Posted: Wed Oct 27, 2021 8:26 am   Subject: SystemC model and OVP environment
The OVP simulator provides information at an instruction level. This can be used to provide some estimations.

The Imperas professional products can be used to obtain information from an executingap ...
  Topic: riscvOVPsimPlus: Page table entry load failed
DuncGrah

Replies: 2
Views: 1672

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 5:19 am   Subject: riscvOVPsimPlus: Page table entry load failed
We have looked at the test case you provided and determined that the problem is that this processor has physical memory protection (PMP) registers, and these have not been set up by Machine mode, so S ...
  Topic: riscvOVPsimPlus: Page table entry load failed
DuncGrah

Replies: 2
Views: 1672

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 12:10 am   Subject: riscvOVPsimPlus: Page table entry load failed
I have sent you a PM with an email address to send a test case so that we can re-produce this issue and provide you a solution.
  Topic: Demo_riscv_RV64GC_Virtio_Linux: Illegal Instruction
DuncGrah

Replies: 1
Views: 1882

PostForum: Ask a Question   Posted: Wed Sep 15, 2021 12:07 am   Subject: Demo_riscv_RV64GC_Virtio_Linux: Illegal Instruction
This appears to be a host program incompatability.

What is the host machine and OS that you are running on?

This error does not appear to be quite the same but are you running a 32-bit OVP progr ...
 
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