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Open Virtual Platforms Forum Index
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  Topic: Is there an option available to halt on illegal: Undecoded
LarryL

Replies: 2
Views: 886

PostForum: Ask a Question   Posted: Thu Jun 30, 2022 1:09 pm   Subject: Is there an option available to halt on illegal: Undecoded
Hi Ravi,

The option you are requesting is not available in riscvOVPsimPlus. However, this capability does exist in the Imperas commercial products, including the ImperasDV products for RISC-V proc ...
  Topic: RISC-V Cannot add U-type instruction
LarryL

Replies: 2
Views: 1052

PostForum: Ask a Question   Posted: Thu Apr 21, 2022 2:03 pm   Subject: RISC-V Cannot add U-type instruction
Hi Jens,

Yes, it seems you have found a shortcoming in the OVP RISC-V model. We are reviewing this issue, and will respond with our recommendations in the next day or two. Most likely we are goin ...
  Topic: Error (RISCV/PK) SYSCALL(unhandled(*))
LarryL

Replies: 11
Views: 2916

PostForum: Ask a Question   Posted: Thu Apr 21, 2022 1:57 pm   Subject: Error (RISCV/PK) SYSCALL(unhandled(*))
Hi RaviB,

The limitations in riscvOVPsimPlus are essentially in two categories. First, there are limitations in the model. Actually, not a lot of limitations there, as the riscvOVPsimPlus RISC-V ...
  Topic: Fault Injection Module (FIM) for ARM v8
LarryL

Replies: 3
Views: 2884

PostForum: Ask a Question   Posted: Thu Oct 14, 2021 11:49 am   Subject: Fault Injection Module (FIM) for ARM v8
Hi Usha,

I will introduce you to our co-authors for the FIM paper. This professor has the FIM module and is interested in collaboration.

Best Regards,

Larry
  Topic: Fault Injection Module (FIM) for ARM v8
LarryL

Replies: 3
Views: 2884

PostForum: Ask a Question   Posted: Mon Oct 11, 2021 10:48 am   Subject: Fault Injection Module (FIM) for ARM v8
Hi UshaJadhav,

Are you referring to the FIM module described in this paper:

https://www.imperas.com/articles/paper-embedded-world-2017-fast-fault-injection-and-simulation-using-virtual-platforms ...
  Topic: Boot Linux Kernel v5.4 on Arm Cortex-A9
LarryL

Replies: 4
Views: 3964

PostForum: Ask a Question   Posted: Mon May 03, 2021 3:50 pm   Subject: Boot Linux Kernel v5.4 on Arm Cortex-A9
Hi Geancarlo,

I think the Device Tree is going to be the key piece of getting the new Linux to boot. Please post here if you have questions on this.

Larry
  Topic: I want to know how to write my own module or peripherals?
LarryL

Replies: 20
Views: 12144

PostForum: Ask a Question   Posted: Mon May 03, 2021 3:48 pm   Subject: I want to know how to write my own module or peripherals?
There are also some good tutorials, including a tutorial on building peripheral models, on the OVP Demos & Videos page https://www.ovpworld.org/demosandvideos.

Larry
  Topic: Boot Linux Kernel v5.4 on Arm Cortex-A9
LarryL

Replies: 4
Views: 3964

PostForum: Ask a Question   Posted: Thu Apr 29, 2021 3:28 pm   Subject: Boot Linux Kernel v5.4 on Arm Cortex-A9
Hi Geancarlo,

Can you provide any more details about your platform? What else is in the virtual platform besides the processor? Is the virtual platform based on one of the OVP example or demo pla ...
  Topic: How to compile c code for the architecture mips
LarryL

Replies: 2
Views: 4575

PostForum: Web Site Help   Posted: Mon Aug 31, 2020 11:21 am   Subject: How to compile c code for the architecture mips
Hi Abhinav,

Is there a specific core that you are targeting?

In any case, probably the best way to get started is with the MIPS demos on the Downloads page: https://www.ovpworld.org/dlp/. Pl ...
  Topic: Compiling Vector Applications for riscvOVPsim
LarryL

Replies: 1
Views: 3765

PostForum: Ask a Question   Posted: Thu Aug 20, 2020 6:41 pm   Subject: Compiling Vector Applications for riscvOVPsim
Hi PsuImc,

Good questions, and I don't have any answers for you. Probably the best approach is to get you into the Imperas University Program and provide you with the Imperas commercial simulator ...
  Topic: regarding ovpsim
LarryL

Replies: 1
Views: 3940

PostForum: Ask a Question   Posted: Mon Jul 15, 2019 3:38 pm   Subject: regarding ovpsim
Currently none of the RISC-V variants provide DSP extensions. Andes Technology have implemented DSP extensions in their A25, AX25 and D25 cores (http://www.andestech.com/en/products-solutions/andesco ...
  Topic: How to observe the number of cycles spent on a c code
LarryL

Replies: 2
Views: 5506

PostForum: Ask a Question   Posted: Tue Feb 12, 2019 8:21 am   Subject: How to observe the number of cycles spent on a c code
For free access to the Imperas professional tools, Imperas has a University Program. Please contact univ [at] imperas [dot] com for more information.

You might also be interested in this paper o ...
  Topic: ARC model availability
LarryL

Replies: 1
Views: 5663

PostForum: Current models   Posted: Wed Jan 09, 2019 9:50 am   Subject: ARC model availability
Hi Michael,

We do have models of the ARC EM6 available, however, there are some restrictions on usage so these are not on the OVP website. If you are interested, please contact me directly and we ...
  Topic: ISS says license expired ...
LarryL

Replies: 4
Views: 10307

PostForum: Licensing   Posted: Tue Feb 06, 2018 5:14 pm   Subject: ISS says license expired ...
Hi AshraIvy,

Can you post the exact message you are getting that says that OVPsim is not working?

Thanks,

Larry
  Topic: Does OVP support the task to preempt the processor?
LarryL

Replies: 1
Views: 6296

PostForum: Getting started   Posted: Wed Aug 16, 2017 1:04 pm   Subject: Does OVP support the task to preempt the processor?
Dear ShenYang,

Anything you can do functionally on the processor can be done with OVP. I am not sure of the exact examples to show what you need, however, these are supported in OVP.

Larry
 
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