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  Topic: queries on register values for branch, multi thread, CSRRW
MannyW

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Thu Aug 18, 2022 9:36 am   Subject: queries on register values for branch, multi thread, CSRRW
Hi Ravi,

Chapter 2.1 of Volume II: RISC-V Privileged Architectures V20211203 says:

Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without ...
  Topic: queries on register values for branch, multi thread, CSRRW
MannyW

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Thu Aug 18, 2022 7:14 am   Subject: queries on register values for branch, multi thread, CSRRW
Hi Ravi,

3. do you have --override riscvOVPsim/cpu/simulateexceptions=T in your command line? Can you share your command line?

Thanks,
Manny
  Topic: queries on register values for branch, multi thread, CSRRW
MannyW

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Wed Aug 17, 2022 7:18 pm   Subject: queries on register values for branch, multi thread, CSRRW
Hi Ravi,

1. I see what you are asking, riscvOVPsim cannot track values of operands. But you can still see the values of s0 and sp, simply scan upward in the output file until you find s0 and sp. ...
  Topic: queries on register values for branch, multi thread, CSRRW
MannyW

Replies: 6
Views: 638

PostForum: Ask a Question   Posted: Tue Aug 16, 2022 7:05 pm   Subject: queries on register values for branch, multi thread, CSRRW
Hi Ravi,

First of all, I don't fully understand question one. What branch related instruction registers are you referring to? When you run riscvOVPsimPlus, with all the traceing turned on, what a ...
  Topic: Is there an option available to halt on illegal: Undecoded
MannyW

Replies: 2
Views: 698

PostForum: Ask a Question   Posted: Thu Jun 30, 2022 10:19 am   Subject: Is there an option available to halt on illegal: Undecoded
Hi Ravi,
Can you provide me more info on your error message? Please PM me.
Thanks,
Manny
  Topic: Unable to dump SD instruction trace information
MannyW

Replies: 10
Views: 1474

PostForum: Ask a Question   Posted: Tue Jun 21, 2022 5:05 pm   Subject: Unable to dump SD instruction trace information
Hi Ravi,
Yes, --tracewrite will not make any difference for sd instructions.

sd instruction is of type S-format, which takes rs1, rs2 and immediate offset. sd instruction does not have desti ...
  Topic: Unable to dump SD instruction trace information
MannyW

Replies: 10
Views: 1474

PostForum: Ask a Question   Posted: Mon Jun 20, 2022 4:24 pm   Subject: Unable to dump SD instruction trace information
Hi Ravi,
"sd" is "store double" which belongs to the load/store type of instructions. I like to suggest that you use command line option:
--tracemem A
to trace all load ...
  Topic: Error (RISCV/PK) SYSCALL(unhandled(*))
MannyW

Replies: 11
Views: 2575

PostForum: Ask a Question   Posted: Thu Apr 21, 2022 5:55 pm   Subject: Error (RISCV/PK) SYSCALL(unhandled(*))
Hi Ravi,

Sorry to hear you were ill, hope you've recovered from it. Let me try to help out here.

-> later versions of riscvOVPsim (you meant to say OVPsimplus only or OVPsim itself has mu ...
  Topic: Error (RISCV/PK) SYSCALL(unhandled(*))
MannyW

Replies: 11
Views: 2575

PostForum: Ask a Question   Posted: Wed Mar 30, 2022 6:30 am   Subject: Error (RISCV/PK) SYSCALL(unhandled(*))
Hi Ravi,
I do not understand the test environment you are using. Can you provide more information on your setup?
  Topic: Unable to initialize SDL
MannyW

Replies: 1
Views: 876

PostForum: Ask a Question   Posted: Tue Mar 22, 2022 7:10 pm   Subject: Unable to initialize SDL
Hi Desh,
Typically "SDL cannot be initialized" happens when the DISPLAY environment variable is not set correctly i.e. the system does not know where to open the new terminal/shell. If thi ...
  Topic: Cortex A57 in 64 bit mode possible with 32 Bit OPV_SIM ?
MannyW

Replies: 2
Views: 1411

PostForum: Getting started   Posted: Thu Feb 24, 2022 11:14 am   Subject: Cortex A57 in 64 bit mode possible with 32 Bit OPV_SIM ?
Hi Georg,
Image for 64 bit architecture compiled with armv8-aarch64.toolchain can be run with either the 64bit OVPsim (you referred as OVP_SIM) or the 32bit OVPsim.
The 32/64 bit of OVPsim refers ...
 
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