Cache and memory different latencies

[MauroMercury]

Hi,

modelling a memory hierarchy (for example cache L1, cache L2 and phisical memory), is there a way to model (and vary) latencies in clock cycles as well, in order to have different load access times?

Thank you.

[LeeMoore]

Hi,

OVPsim is an instruction accurate simulator, not a cycle accurate simulator. It is possible to model the contents and tags of various caches, but not the performance issues associated with their operation.
In order to get cycle accurate performance measurements there are more issues to consider such as the processor pipeline, out of order accesses... etc

Thx
Lee Moore