Uncachable memory

[MauroMercury]

Hi,

I've been trying to model a single level of cache memory using the default model available in OVP. Since I need to make only part of the main-bus address space cachable, I used a Bridge to partition the address space, cascaded with a full MMC. This solved the functional problem but reduced heavily simulation perfomance. Is there a way to have a better trade off, keeping this functionality and higher perfomance, for example using a transparent MMC connected on a bus instead of directly to a processor?

Thank you very much,
Mauro

[JimStraus]

Hi Mauro,

It sounds like what you are describing should not have any additional overhead for the non-cached addresses.

Do you think that you are seeing the simulation performance for the non cached accesses decreased as well? Have you done some experiments to verify this - such as adding the cache but never accessing any of the memory addresses that it is connected to?

MMCs will greatly reduce simulation performance, so even if only some addresses are handled by the MMC you could still see a very large slow down.

Jim Straus