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AntonioPrioletti
Joined: 02 May 2011 Posts: 20
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Posted: Fri Sep 16, 2011 7:34 am Post subject: Shared Cache |
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Hi, I would suggest a problem. I have created an architecture with two processors, and I instanced a cache full privacy for both processors, and then a cache shared by connecting it always full to the first two via a single bus for sharing. Now if I make a call before the main application where a variable x-volatile, then the processor assigns the value 0 3. When I go to read the value of the variable x with the processor 1 this is always 0 and not 3 because the processor 0 has changed. Looking at the address of the variable x that coincides for both variables, then how come I always value 0? :cry: |
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AntonioPrioletti
Joined: 02 May 2011 Posts: 20
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Posted: Fri Sep 16, 2011 1:31 pm Post subject: Re: Shared Cache |
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Sorry, but in precedent post I wrote a really poor english, because I am Italian; now think that it is better.
Hi, I would suggest a problem. I have created an architecture with two processors, and I instanced a full private cache for both processors, and then a shared cache of second level always full, by connecting it with the first via a single share bus. Now a create an example application when I define a volatile variable x, then the processor 0 assigns to it the value 3. When I go to read the value of the variable x with the processor 1 this is always 0 and not 3 though the processor 0 has changed that value in 3. Looking at the address of the variable x in both processor, that coincides, How can i solve this problem, doing so that the processor 1 read value 3 and not 0?
The code is:
volatile int x;
int proc0(int id)
{
printf("Cpu 0, before change x = %d \n", x);
x = 3;
printf("Cpu 0, after change x = %d, with address %p\n", x, &x);
}
int proc1(int id)
{
printf("Cpu 1, before change x = %d, with address %p\n", x, &x);
x = 20;
printf("Cpu 1, after change x = %d\n", x);
}
int main(int argc, char **argv) {
int id = impProcessorId();
printf("CPU %d starting...\n", id);
switch(id) {
case 0:
proc0(id);
break;
case 1:
proc1(id);
break;
case 2:
break;
}
return 1;
} |
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DuncGrah OVP Technologist

Joined: 27 Feb 2008 Posts: 1646 Location: United Kingdom
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Posted: Fri Oct 07, 2011 5:44 am Post subject: |
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This is the issue of using writeback rather than write through caches as discussed in this forum posting. |
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