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porting example customProcessorTrace to RISC-V

 
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IztokJeras



Joined: 07 Nov 2018
Posts: 5

PostPosted: Sun Nov 18, 2018 10:22 am    Post subject: porting example customProcessorTrace to RISC-V Reply with quote

The example Examples/SimulationControl/customProcessorTrace is designed to run OR1K code, and I would like to port it to run RISC-V code.

First I changed example.sh:
Code:

CROSS=RISCV32


Then I had to install install.pkg to:
Code:

install microsemi_riscv.toolchain


The next step would be to modify module/module.op.tcl:
Code:

ihwnew -name simpleCpuMemory

ihwaddbus -instancename mainBus -addresswidth 32

ihwaddprocessor -instancename cpu1 \
                -vendor ovpworld.org -library processor -type or1k -version 1.0 \
                -variant generic \
                -semihostname or1kNewlib
ihwconnect -bus mainBus -instancename cpu1 -busmasterport INSTRUCTION
ihwconnect -bus mainBus -instancename cpu1 -busmasterport DATA

ihwaddmemory -instancename ram1 -type ram
ihwconnect -bus mainBus -instancename ram1 -busslaveport sp1 -loaddress 0x0 -hiaddress 0xffffffff


I attempted to set -type to riscv, but I had no idea about what to set -semihostname to, so I removed this option. Is semihosting even available on RISC-V?

After running example.sh I get the next error:
Code:

Error (VLNV_MV) VLNV reference (ovpworld.org/processor/riscv/1.0/model.so) found 0 matches.


Regards,
Iztok Jeras
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1639
Location: United Kingdom

PostPosted: Mon Nov 19, 2018 3:30 am    Post subject: Reply with quote

I would suggest you use one of the following
To see all the models available in the library
Code:
$IMPERAS_ISS --showlibrary

To see only the processor models
Code:
$IMPERAS_ISS --showlibraryprocessors


You should then see that the RISC-V processor model is available at VLNV riscv.ovpworld.org/processor/riscv/1.0
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