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initsp=0 did not match anything in the platform

 
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JonathanJonsson



Joined: 04 Jul 2022
Posts: 5
Location: Gothenburg

PostPosted: Mon Jul 11, 2022 4:08 am    Post subject: initsp=0 did not match anything in the platform Reply with quote

Hi! This may be a simple question but I'm trying to initialize the stack pointer in accordance to the bootloader of the CPU I'm testing.
I am using OVPsim plus version: 20220527.0 and its corresponding user guide states that the following override is available:
"--override riscvOVPsim/cpu/pk/initsp=0 (Uns64) (default=0) (default) Stack Pointer initialization"

However I can't get this to work for RV64GCB since:
'--override riscvOVPsim/cpu/pk/initsp=0' did not match anything in the platform

I also tried tried running with "-showoverrides" and initsp was listed as an option.

Am I missing some flag or something else to enable these overrides?
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DuncGrah
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PostPosted: Tue Jul 12, 2022 4:01 am    Post subject: Reply with quote

Hi,
Can you provide the actual command line that you are using. When I try to apply an override for initsp it is working as expected.

I am wondering if perhaps you got the syntax incorrect?

When I run

Quote:

../../bin/Linux64/riscvOVPsimPlus.exe --program fibonacci.RISCV64.elf --variant RVB64I --override riscvOVPsim/cpu/add_Extensions=MACSU --override riscvOVPsim/cpu/pk/initsp=1 --trace --tracechange


I see for the initial access to the stack pointer

Quote:

Info 'riscvOVPsim/cpu', 0x00000000000126d6(__register_exitproc): 7179 addi sp,sp,-48
Info sp 0000000000000001 -> ffffffffffffffd1
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JonathanJonsson



Joined: 04 Jul 2022
Posts: 5
Location: Gothenburg

PostPosted: Tue Jul 12, 2022 4:13 am    Post subject: Reply with quote

DuncGrah wrote:
Hi,
Can you provide the actual command line that you are using. When I try to apply an override for initsp it is working as expected.

I am wondering if perhaps you got the syntax incorrect?

When I run

Quote:

../../bin/Linux64/riscvOVPsimPlus.exe --program fibonacci.RISCV64.elf --variant RVB64I --override riscvOVPsim/cpu/add_Extensions=MACSU --override riscvOVPsim/cpu/pk/initsp=1 --trace --tracechange


I see for the initial access to the stack pointer

Quote:

Info 'riscvOVPsim/cpu', 0x00000000000126d6(__register_exitproc): 7179 addi sp,sp,-48
Info sp 0000000000000001 -> ffffffffffffffd1


Hi, thanks for the reply!

The following command is what I run, removing the initsp override allows me to execute the program as expected, which makes me think that the control file is not at fault. I'll post it too if of relevance.

Quote:

./riscvOVPsimPlus.exe --controlfile $r_dv/target/rv64_gcb//riscvOVPsim.ic --objfilenoentry $r_dv/out/asm_test/riscv_loop_test_2022-07-12_10\:56\:52_0.o --override riscvOVPsim/cpu/pk/initsp=1 --override riscvOVPsim/cpu/simulateexceptions=T --trace --tracechange --traceshowicount --tracemode --traceregs --finishafter 100000
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DuncGrah
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PostPosted: Tue Jul 12, 2022 4:54 am    Post subject: Reply with quote

I notice that you have added "-override riscvOVPsim/cpu/pk/initsp=1" from my example execution command line, this will likely cause an error during simulation as the SP is not aligned. I was simply using this as an example to show the SP changes from an initial value set using this override.
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JonathanJonsson



Joined: 04 Jul 2022
Posts: 5
Location: Gothenburg

PostPosted: Tue Jul 12, 2022 5:27 am    Post subject: Reply with quote

DuncGrah wrote:
I notice that you have added "-override riscvOVPsim/cpu/pk/initsp=1" from my example execution command line, this will likely cause an error during simulation as the SP is not aligned. I was simply using this as an example to show the SP changes from an initial value set using this override.


DuncGrah wrote:
I notice that you have added "-override riscvOVPsim/cpu/pk/initsp=1" from my example execution command line, this will likely cause an error during simulation as the SP is not aligned. I was simply using this as an example to show the SP changes from an initial value set using this override.


Yes, however I am not reaching the simulation, the intention is to initialize initsp to 0x10000 which is aligned but even when setting the proper value I keep getting the message "did not match anything in the platform".
Quote:

--variant RV64GCB
--override riscvOVPsim/cpu/misa_MXL=2
#--override riscvOVPsim/cpu/misa_MXL_mask=0x0 #outdated override
--override riscvOVPsim/cpu/misa_Extensions_mask=0x0 # 0
--override riscvOVPsim/cpu/unaligned=F
--override riscvOVPsim/cpu/mtvec_mask=0x0 # 0
--override riscvOVPsim/cpu/user_version=2.3
--override riscvOVPsim/cpu/priv_version=1.11
--override riscvOVPsim/cpu/mvendorid=0
--override riscvOVPsim/cpu/marchid=0
--override riscvOVPsim/cpu/mimpid=0
--override riscvOVPsim/cpu/mhartid=0
--override riscvOVPsim/cpu/cycle_undefined=F
--override riscvOVPsim/cpu/instret_undefined=F
--override riscvOVPsim/cpu/time_undefined=T
--override riscvOVPsim/cpu/reset_address=0x00000000
--override riscvOVPsim/cpu/simulateexceptions=T
--override riscvOVPsim/cpu/defaultsemihost=F
--override riscvOVPsim/cpu/wfi_is_nop=T
--override riscvOVPsim/cpu/PMP_grain=10 #(Uns32) (default=0) (default) Specify PMP region granularity, G (0 => 4 bytes, 1 => 8 bytes, etc)
--override riscvOVPsim/cpu/PMP_registers=16 #(Uns32) (default=16) (default) Specify the number of implemented PMP address registers
--override riscvOVPsim/cpu/Zbe=F
--override riscvOVPsim/cpu/Zbf=F
--override riscvOVPsim/cpu/Zbm=F
--override riscvOVPsim/cpu/Zbp=F
--override riscvOVPsim/cpu/Zbr=F
--override riscvOVPsim/cpu/Zbt=F
#--override riscvOVPsim/cpu/pk/initsp=0 #65536 #(Uns64) (default=0) (default) Stack Pointer initialization, altered to reflect that of the bootloader initialize SP to 0x10000
--exitonsymbol _exit

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DuncGrah
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PostPosted: Wed Jul 13, 2022 12:05 am    Post subject: Reply with quote

Can you provide this example to me? I would like to run here. I would also need the details of the version, what you installed etc.
I will PM my personal email to use if you can.
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DuncGrah
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PostPosted: Wed Jul 13, 2022 6:53 am    Post subject: Reply with quote

Once I ran the example I saw the same behaviour as you are seeing.

It then became obvious that this is caused because you are disabling the default semihost (PK), which provides this feature, in your control file.

By default semihosting is enabled "defaultsemihost=T" in the riscvOVPsimPlus platform but by adding the following line into your control file this is disabled.
Quote:
-override riscvOVPsim/cpu/defaultsemihost=F


The question is, have you disabled the semihosting because it provides behaviour you do not want? The PK semihost library will intercept the ecall instruction and provide the required system behaviour.

You can see by using --showoverrides with/without the defaultsemihost setting that the initsp parameter is part of the pk library installed on the processor model and is only available when that is available.
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JonathanJonsson



Joined: 04 Jul 2022
Posts: 5
Location: Gothenburg

PostPosted: Wed Jul 13, 2022 10:52 pm    Post subject: Reply with quote

DuncGrah wrote:
Once I ran the example I saw the same behaviour as you are seeing.

It then became obvious that this is caused because you are disabling the default semihost (PK), which provides this feature, in your control file.

By default semihosting is enabled "defaultsemihost=T" in the riscvOVPsimPlus platform but by adding the following line into your control file this is disabled.
Quote:
-override riscvOVPsim/cpu/defaultsemihost=F


The question is, have you disabled the semihosting because it provides behaviour you do not want? The PK semihost library will intercept the ecall instruction and provide the required system behaviour.

You can see by using --showoverrides with/without the defaultsemihost setting that the initsp parameter is part of the pk library installed on the processor model and is only available when that is available.


Thank you for the reply.

Alright that explains the conundrum, I can now select the option initsp. However, the semihost option was disabled by default with riscv-dv and it seems like it gives some undesired behavior to leave it active. One example is a riscv-dv ebreak test, if semihost=T the simulation yields an error (unhandled syscall) and exits at the first ebreak call. The intention however, is to continue on to the mtvec_handler and from there to the ebreak_handler. I think I'll have have to leave semihost=F and find an alternative solution instead.
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DuncGrah
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PostPosted: Thu Jul 14, 2022 3:33 am    Post subject: Reply with quote

I understand the situation, where semihosting is enabled to handle a particular set of system calls, and is very useful for host/user interaction, it can get in the way when the application (test) wants these same instructions to execute within the application.
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