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queries on register values for branch, multi thread, CSRRW

 
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RaviB



Joined: 16 Mar 2022
Posts: 27

PostPosted: Tue Aug 16, 2022 6:25 am    Post subject: queries on register values for branch, multi thread, CSRRW Reply with quote

Hi,

Request help on following aspects.

1.
Quote:
Can I can dump register values for branch related instructions?
I get to see for beq, blt, etc. I'm unable to generate registers values at that point as of now.


2.
Quote:
Does OVPsimplus support multi thread execution?
I get to see Error (CM_FNS) Flag '--parallelthreads' not supported in this product.


3.
Quote:
Consider Instruction "csrrw a0,misa,a1". Though misa is not writable, we are trying to update misa with value in a1. It just ignores write to misa and proceeds further.
I have another instruction "csrrw a0,mvendorid,a1" where mvendorid is also not writable for me. In this case, OVPsimplus throws "CSR has no write access" and stops executing.
What need to be done to continue execution of following instructions after this without error just like in misa case? If throwing error is correct, why misa case did not throw this kind of error?


Thanks in advance.

Regards,
Ravi
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MannyW



Joined: 14 Apr 2019
Posts: 11

PostPosted: Tue Aug 16, 2022 7:05 pm    Post subject: Reply with quote

Hi Ravi,

First of all, I don't fully understand question one. What branch related instruction registers are you referring to? When you run riscvOVPsimPlus, with all the traceing turned on, what are you getting? And what do you want to get?


For multi thread, here is an override you can use:
--override riscvOVPsim/parallelthreads=<nn>
But I think this maybe a core dependent thing, not totally sure. To find out whether this feature is available for your riscv configuration, add --showoverrides on your command line, the simulation will generate the list of overrides available. I believe you should find this parallelthreads in there.


The mvendorid CSR is a read-only register for encoding the manufacturer of the part. Whereas the misa CSR is a read-write register.
Having said that, you can set the mvendorid value by using override on the command line, like this:
--override riscvOVPsim/cpu/mvendorid=<value>


Regards,
Manny
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RaviB



Joined: 16 Mar 2022
Posts: 27

PostPosted: Tue Aug 16, 2022 9:42 pm    Post subject: Reply with quote

Hi Manny,

Hope you are good. Thanks for your response.

1. Consider "beq s0,sp,167074994fa0". I'm using trace options "--trace --tracewrite --tracechange --tracemode --tracemem A --traceshowicount".
But it doesn't dump any information in log for branch related instructions.
Quote:
It just shows:
Info 232: 'riscvOVPsim/cpu', 0x0000167074994fac(main+c): Machine fe240ae3 beq s0,sp,167074994fa0

I wanted to track values of registers (ex: s0,sp in this case). Same applies to all branch related instructions. Is it possible to dump values of registers at that instant?

2. I tried using "riscvOVPsimPlus.exe --program rs64.elf --showmodeloverrides | grep "parallelthreads""
But, there isn't any listed. I'm currently using "riscvOVPsimPlus with IMPERAS RV32/64 I,M,C base tests and B Bitmanip tests" package of OVPsimplus.
If this has no support, Can you suggest which to use that has bitmanip suppost also?

3. Yes, I'm using the override "--override riscvOVPsim/cpu/mvendorid=". But may I know what happens when we are trying to write to a read only register? I meant does it tries to invoke any handlers (exception handler or interrupt handler) If not any handlers, what exactly is expected in terms of behavior?
Just to know if there is a way to bypass error and continue execution.

Thanks for all the patience in going through.

Regards,
Ravi
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MannyW



Joined: 14 Apr 2019
Posts: 11

PostPosted: Wed Aug 17, 2022 7:18 pm    Post subject: Reply with quote

Hi Ravi,

1. I see what you are asking, riscvOVPsim cannot track values of operands. But you can still see the values of s0 and sp, simply scan upward in the output file until you find s0 and sp.

2. my apology, if it is not listed, then it is not supported.


Manny
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MannyW



Joined: 14 Apr 2019
Posts: 11

PostPosted: Thu Aug 18, 2022 7:14 am    Post subject: Reply with quote

Hi Ravi,

3. do you have --override riscvOVPsim/cpu/simulateexceptions=T in your command line? Can you share your command line?

Thanks,
Manny
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RaviB



Joined: 16 Mar 2022
Posts: 27

PostPosted: Thu Aug 18, 2022 7:22 am    Post subject: Reply with quote

Hi Manny,

Yes, I have it in my run command. But we have disabled exception handler for now. Just wanted to understand the behavior if write to Read only register will try to raise an exception or interrupt.

Regards,
Ravi
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MannyW



Joined: 14 Apr 2019
Posts: 11

PostPosted: Thu Aug 18, 2022 9:36 am    Post subject: Reply with quote

Hi Ravi,

Chapter 2.1 of Volume II: RISC-V Privileged Architectures V20211203 says:

Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.

riscvOVPsimPlus adheres to the specification above. When your instruction tried to write to the read-only mvendorid CSR while simulateexceptions is disabled, the simulator cannot continue. So, it exits after printing the message.

Regards,
Manny
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