Cache statististics

YasirQadri · Joined: 10 Jul 2008 Posts: 4 Location: UK

Has the cache model been implemented in any of the processor models. If yes can we have a report of number of cache hits/miss out of it.

MatthewHall · OVP Technologist Joined: 26 Feb 2008 Posts: 84

Yasir,
None of the processor models that I know of have a 'close-coupled' cache (that is, a cache which responds to the processor's cache-control instructions). However, OVPsim is shipped with a range of generic cache models and several example platforms which use them. All the cache models report their hits and misses at the end of simulation.

The cache models are in the OVPsim download in
ImperasLib/source/ovpworld.com/mmc

In the Examples directory, take a look at
Examples/Platforms/cascadedTransparentMMC
and
Examples/Platforms/transparentMMC

DuncGrah · Posted: Fri Feb 20, 2009 12:34 am Post subject:

Just to be clear, if you add one of the generic cache models (they can be added separately on instruction and data buses) you will be provided with the cache statistics you are looking for ie hits and misses.

AwaisYousaf · Posted: Mon Sep 20, 2010 10:37 pm Post subject: Default vs generic caches

DuncGrah · Posted: Tue Sep 21, 2010 1:20 am Post subject:

In OVP the MMC can be used to provide a generic cache model but, as you point out, this does not take into account the cache instructions that may be used by a program to lock or flush cache lines or other such functions.

The processor model can be extended to include the cache or signal cache instructions execution.