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Cache statististics

 
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YasirQadri



Joined: 10 Jul 2008
Posts: 4
Location: UK

PostPosted: Fri Feb 13, 2009 10:02 am    Post subject: Cache statististics Reply with quote

Has the cache model been implemented in any of the processor models. If yes can we have a report of number of cache hits/miss out of it.
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MatthewHall
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Joined: 26 Feb 2008
Posts: 84

PostPosted: Mon Feb 16, 2009 1:23 am    Post subject: Yes and No. Reply with quote

Yasir,
None of the processor models that I know of have a 'close-coupled' cache (that is, a cache which responds to the processor's cache-control instructions). However, OVPsim is shipped with a range of generic cache models and several example platforms which use them. All the cache models report their hits and misses at the end of simulation.

The cache models are in the OVPsim download in
ImperasLib/source/ovpworld.com/mmc

In the Examples directory, take a look at
Examples/Platforms/cascadedTransparentMMC
and
Examples/Platforms/transparentMMC
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DuncGrah
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Joined: 27 Feb 2008
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PostPosted: Fri Feb 20, 2009 12:34 am    Post subject: Reply with quote

Just to be clear, if you add one of the generic cache models (they can be added separately on instruction and data buses) you will be provided with the cache statistics you are looking for ie hits and misses.
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AwaisYousaf



Joined: 02 Mar 2010
Posts: 63
Location: U-E-T Lahore, Pakistan

PostPosted: Mon Sep 20, 2010 10:37 pm    Post subject: Default vs generic caches Reply with quote

DuncGrah wrote:
Just to be clear, if you add one of the generic cache models (they can be added separately on instruction and data buses) you will be provided with the cache statistics you are looking for ie hits and misses.



Can i get the cache statistics of default processor's 'close coupled' caches which responds to the processor's cache-control instructions. I don't want to use generic caches as modeled in examples in C:\Imperas\Examples\Platforms Waiting for any response.
Awais Yousaf
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DuncGrah
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Location: United Kingdom

PostPosted: Tue Sep 21, 2010 1:20 am    Post subject: Reply with quote

In OVP the MMC can be used to provide a generic cache model but, as you point out, this does not take into account the cache instructions that may be used by a program to lock or flush cache lines or other such functions.

The processor model can be extended to include the cache or signal cache instructions execution.
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