Cache coherence, cache miss/hit cache levels

[fadi.edward]

Since your design hasn't been release yet for nor of the processor, can you please discuss a little your cache coherence scheme, is it the same for all the processors.

Is what you are showing in the "OVPsim_arm7_multicore2" demo is a 2 level cache system?

What happens in case of a cache miss, or L1 Cache update (is it a write-through)?

Will the simulator code will be available in case someone wants to make a change in the implementation of this module?

[JamesKenney]

The demos we're showing on the website don't have caches associated with the processors, but we do have technology available for modelling caches at different levels using our MMC (memory model component) technology.

Using an MMC, you can model cache behavior at two different levels:
1. Transparent MMC: this allows modelling of things like cache tags while leaving the actual memory content to be modeled by the simulator. This is good if you want to get (for example) hit/miss rates in an L1 cache without degrading performance much.
2. Full MMC: for caches, this allows modeling of both tags and content, which you will need to do if you have incoherent caches and you care about modeling those incoherencies in your multiprocessor simulation.

In terms of performance, on my 3Ghz PC, I expect to see several hundred MIPS simulation speeds for simulations without caches (like the demos), 50-100 MIPS when I have transparent MMCs recording cache hits/misses and 10-20 MIPS when I have full MMCs, although this is of course highly dependent on the complexity of the MMC model (and see the caveat at the end of this post).

Like other OVPsim components, MMCs are designed to be separately-instantiatable, so you can decide whether or not you want them in your simulation. You can instantiate them in series, so for example you can have two L1 MMC transparent cache models feeding into an L2 MMC full model if you wish.

One final caveat about these performance numbers: OVPsim isn't trying to be a cycle-accurate simulator - we're aiming at the instruction-accurate application development space. To get the speeds I've quoted above, each processor in a multiprocessor system needs to be run for a reasonable time slice (say, hundreds of thousands of instructions) before moving on to the next. If the system contains shared caches, then this obviously distorts the content of the shared cache unrealistically (it will first be populated almost entirely with data required by the first processor, then repopulated with data for the second, and so on). It is certaily possible to make OVPsim test harnesses that step invidual processors in a multiprocessor system a single instruction at a time to stimulate the cache more realistically, but performance will then be dominated by the harness and switching time, and you would probably get only 1-5 MIPS.

[JamesKenney]

I omitted a reply to the last part of your question: we will certainly post model source, and we hope that others in the community will too as new models are developed. So you will certainly be able to modify these models to change behavior if you wish.