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OVPsim SEGV handler in Cadence systemC simulator
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GregoryAugier



Joined: 19 Jul 2011
Posts: 6

PostPosted: Wed Jul 27, 2011 2:49 pm    Post subject: OVPsim SEGV handler in Cadence systemC simulator Reply with quote

I'm new to this forum and OVP in general.

I am having problems elaborating the OVP-TLM2.0 example in the Cadence NC-SC environment, due to a SEGV violation.

I read in an other thread on this forum the following comment :

"The reason for this, is that the simulator uses the SEGV signal as part of its normal operation (it has its own handler). "

When debugging with gdb, it is adviced to disable the handling of SIGSEGV by the debugger. However, I can't prevent the Cadence elaboration to intercept this signal and abort the elaboration.

Was it ever attempted to compile the OVP example in the Cadence systemC simulator ? Is there any workaround in OVPsim to deal with this issue ?

Thanks,

Gregory
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LeeMoore
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Joined: 27 Feb 2008
Posts: 635

PostPosted: Thu Jul 28, 2011 1:19 pm    Post subject: Reply with quote

Hi Gregory

Let me see if I can provide some help.

Firstly, which TLM demo are you referring to, we have many TLM demos, please let me know the name of the directory.

The OVPsim simulator only uses the SEGV signal and handler during simulation. Are you saying the SEGV occurs during elaboration ?
I would suggest running under a debugger in order to see what is happening at the point where the SEGV happens.

Cadence have many of the TLM examples working in the cadence environment, but we can ask them specifically if we know which exact demo you are attempting to run.

Finally what operating system are you running and is it 32 bit or 64 bit Linux ?

Thx
Lee
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GregoryAugier



Joined: 19 Jul 2011
Posts: 6

PostPosted: Thu Jul 28, 2011 2:26 pm    Post subject: Reply with quote

Hi Lee,

I'm running the following example Imperas.20110427/Examples/Platforms/SystemC_TLM2.0 on on 64bit Linux.

FYI, I have no issue to compile & exec the demo with the OSCI systemC. My issues only occurs when I try in the Cadence Incisive 9.2 platform.

You are correct, the SEGV normally occurs during simulation, but it seems the behavior of the cadence elaboration (ncelab) is to dynamically link the systemC env during elab as a sanity check (i.e binding errors,..), without invoking sc_start()

Here is the resulting log from ncelab that shows that OVPsim is invoked during this stage :

Quote:

ncelab -loadsc ./platform_cpp/platform.Linux.so sc_main
ncelab: 09.20-s013: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
Constructing.

OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Thu Jul 28 15:11:46 2011


Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/sw/st_division/dsd/soft/imperas/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/sw/st_division/dsd/soft/imperas/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/sw/st_division/dsd/soft/imperas/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
ncelab: *E,SIGUSR: Unix Signal SIGSEGV raised from user application code.
ncelab: *W,SCK1026: sc_main() did not call a simulation control construct like sc_start() in ncelab; design elements instantiated in sc_main are unknown to ncelab and will cause simulation to fail
In file: sc_cosim.cpp:2938.

I did debug using gdb during my investigation, and confirmed that the SEGV is intercepted by ncelab, and interpreted as an error code that aborts the right process of elaboration.

Included below is the gdb tack trace after the SEGV is issued.

Quote:

#0 0xf6fc3af3 in icmlIfsGetHostId () from /sw/st_division/dsd/soft/imperas/Imperas.20110427/bin/Linux/libOVPsim.so
#1 <signal handler called

#2 __dynamic_cast (src_ptr=0xee5fa90e, src_type=0xf777ec6c, dst_type=0xf7a6fde0, src2dst=-1) at /glad/sfi/ct_src/gcc-v4.1.2/platforms/rh32/matrix_bootstrap_000/gcc-4.1.2/libstdc++-v3/libsupc++/tinfo.cc:124
#3 0xf7a43ebc in sc_core::sc_port_b<tlm::tlm_fw_transport_if<tlm> >::add_interface (this=0xf6bb8a98, interface_=0xee5fa90e)
at /sw/st_division/dsd/soft/cadence/incisiv/92usr3/IUS92/tools/systemc/include_pch/sysc/communication/sc_port.h:666
#4 0xf758d598 in sc_core::sc_port_base::bind () from /sw/st_division/dsd/soft/cadence/incisiv/92usr3/IUS92/tools/systemc/lib/libsystemc_sh.so
#5 0xf7a44731 in sc_core::sc_port_b<tlm::tlm_fw_transport_if<tlm> >::operator() (this=0xf6bb8a98, interface_=@0xf6bb8220)
at /sw/st_division/dsd/soft/cadence/incisiv/92usr3/IUS92/tools/systemc/include_pch/sysc/communication/sc_port.h:377

I can take this issue to the Cadence support, but it seems to me more related to the way OVPsim deals with the SEGV than an issue with NC-Elab itself.
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LeeMoore
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Posts: 635

PostPosted: Fri Jul 29, 2011 3:13 am    Post subject: Reply with quote

Hi Gregory,

I have asked one of the engineers from Cadence to take a look at this issue. Hopefully he will post something on the forum to identify the issue.

Thx
Lee
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DaveVonBank



Joined: 22 Sep 2008
Posts: 4

PostPosted: Mon Aug 01, 2011 10:46 pm    Post subject: Reply with quote

Hi Gregory / Lee,

I'm able to run Imperas.20110427/Examples/Platforms/SystemC_TLM2.0 on 64bit Linux using Cadence Incisive 9.2. There are two caveats:
- I'm using 09.20-s034, not 09.20-s013 as Gregory used. I wasn't able to easily find an earlier version.
- I'm using CpuManager rather than OVPSim as the OVP simulator because I don't have a license for OVPSim. I'm working on the Cadence team that is integrating Cadence SystemC with OVP (the Virtual System Platform product). This integration requires the enhanced ICM debug interfaces available with CpuManager; so that is the license we have.
One or both of these must be the reason why things run for me but not Gregory.

Regards,
Dave

Here's what I did:

# Configured my account for the 20110427 OVP release from Imperas.

cd <somedir>
cp -r $IMPERAS_HOME/Examples/Platforms/SystemC_TLM2.0 .
cd SystemC_TLM2.0
make -C application
cd platform_cpp

# edited platform.cpp to derive class simple from sc_module; until I
# made this change, 09.20-s034 gave me:
# *E,SCK512: incorrect use of sc_module_name
# this is because, per section 5.3.3 of the IEEE 1666-2005 LRM, it is
# illegal to use sc_module_name in a constructor of class simple without
#simple being derived from sc_module

##############################################
# compile/link the design without elaborating to use the same
# step for elaborating as did Gregory; this creates libncsc_model.so
# note that if "-stop link" is removed below the example is successfully
# compiled, linked, elaborated, and run all in one step
ncsc_run -stop link -f run_ovp.f +systemc_args+../application/int.elf platform.cpp

# where run_ovp.f is:
-I$IMPERAS_HOME/ImpPublic/include/host
-I$IMPERAS_HOME/ImperasLib/source
-DSC_INCLUDE_DYNAMIC_PROCESSES
$IMPERAS_HOME/ImperasLib/source/ovpworld.org/modelSupport/tlmPlatform/1.0/tlm2.0/tlmPlatform.cpp
$IMPERAS_HOME/ImpPublic/source/host/icm/icmCpuManager.cpp
$IMPERAS_HOME/ImperasLib/source/ovpworld.org/modelSupport/tlmProcessor/1.0/tlm2.0/tlmProcessor.cpp
$IMPERAS_HOME/ImperasLib/source/ovpworld.org/modelSupport/tlmMMC/1.0/tlm2.0/tlmMmc.cpp
$IMPERAS_HOME/ImperasLib/source/ovpworld.org/modelSupport/tlmPeripheral/1.0/tlm2.0/tlmPeripheral.cpp
$IMPERAS_HOME/ImperasLib/source/ovpworld.org/memory/ram/1.0/tlm2.0/tlmMemory.cpp
-L$IMPERAS_HOME/lib/Linux/External/lib
-L$IMPERAS_HOME/bin/Linux
-lRuntimeLoader
-ldl
-lpthread

#############################################
# elaboration step passing the elf file as an argument to sc_main
ncelab -loadsc ./libncsc_model.so sc_main +systemc_args+../application/int.elf
ncelab: 09.20-s034: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
Constructing.


CpuManager v20110427.0 Platform simulator from www.imperas.com.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
CpuManager started: Tue Aug 2 01:58:47 2011


Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.


#############################################
# run step passing the elf file as an argument to sc_main
ncsim sc_main +systemc_args+../application/int.elf
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GregoryAugier



Joined: 19 Jul 2011
Posts: 6

PostPosted: Tue Aug 02, 2011 9:20 am    Post subject: Reply with quote

Hi Dave,

thanks for looking into my issue.

First, let me comment about the LRM compliance issue:

I did face it as well, and was able to workaround it. One point worth mentionning is that in my case, platform.cpp was not the only place I needed to modify to get rid of the error seen in ncelab. This issue is also raising some concerns of mine, as of why this error in not reported by the OSCI version (I verified, the code is there in the 2.2.0 OSCI source as well). I think a separate thread should be open to discuss about this compliance issue.

Now, about my SEGV issue:

I followed your instructions step by step, and still getting the SEGV error as before. I will now install and try with the latest 9.2 update, but my gut feeling tells me that it could be differences of behavior between OVPsim and CpuManager.
Lee, could you investigate this point ?

I'll keep you both posted on the trial with latest 9.2

Regards

Gregory
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GregoryAugier



Joined: 19 Jul 2011
Posts: 6

PostPosted: Wed Aug 03, 2011 10:43 am    Post subject: Reply with quote

same issue with latest 9.2 (usr11)

Quote:

ncelab: 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
Constructing.


OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Wed Aug 3 11:34:12 2011


Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/sw/st_division/dsd/soft/imperas/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/sw/st_division/dsd/soft/imperas/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/sw/st_division/dsd/soft/imperas/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
ncelab: *E,SIGUSR: Unix Signal SIGSEGV raised from user application code.
ncelab: *W,SCK1026: sc_main() did not call a simulation control construct like sc_start() in ncelab; design elements instantiated in sc_main are unknown to ncelab and will cause simulation to fail
In file: sc_cosim.cpp:2999.
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DaveVonBank



Joined: 22 Sep 2008
Posts: 4

PostPosted: Wed Aug 03, 2011 11:58 am    Post subject: Reply with quote

So for release 20110427, OVPSim has a problem, while CpuManager does not. I recall discussing the proper chaining of signal handlers with Imperas in the context of integrating OVP simulators with Incisive. Perhaps changes were made in CPUManager for this, but these didn't make their way into OVPSim. Is this a possibility?
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DuncGrah
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Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Mon Aug 08, 2011 5:42 am    Post subject: Reply with quote

Since the 20110427.0 release when the simulator (OVPsim or CpuManager) catches a SIGSEGV that did NOT originate in the simulator scheduler, the signal is passed to any previously installed handler. Thus, a Cadence handler should receive the signal. (If Cadence code installs a handler later than OVP, we exepct the Cadence code to do the same as OVP and to pass unexpected signals to any previously installed handler).

We do not expect any differences in signal handling between OVPsim and CpuManager

This does not appear to be the problem in this case!

Reading the stack trace :

Quote:
#0 0xf6fc3af3 in icmlIfsGetHostId () from /sw/st_division/dsd/soft/imperas/Imperas.20110427/bin/Linux/libOVPsim.so
#1 <signal handler called
#2 __dynamic_cast (src_ptr=0xee5fa90e, src_type=0xf777ec6c, dst_type=0xf7a6fde0, src2dst=-1) at /glad/sfi/ct_src/gcc-v4.1.2/platforms/rh32/matrix_bootstrap_000/gcc-4.1.2/libstdc++-v3/libsupc++/tinfo.cc:124
#3 0xf7a43ebc in sc_core::sc_port_b<tlm::tlm_fw_transport_if<tlm> >::add_interface (this=0xf6bb8a98, interface_=0xee5fa90e)
at /sw/st_division/dsd/soft/cadence/incisiv/92usr3/IUS92/tools/systemc/include_pch/sysc/communication/sc_port.h:666
#4 0xf758d598 in sc_core::sc_port_base::bind () from /sw/st_division/dsd/soft/cadence/incisiv/92usr3/IUS92/tools/systemc/lib/libsystemc_sh.so
#5 0xf7a44731 in sc_core::sc_port_b<tlm::tlm_fw_transport_if<tlm> >::operator() (this=0xf6bb8a98, interface_=@0xf6bb8220)
at /sw/st_division/dsd/soft/cadence/incisiv/92usr3/IUS92/tools/systemc/include_pch/sysc/communication/sc_port.h:377


This looks like a crash occurring during the connection of ports in the elaboration phase.
We think the symbol in libOVPsim is is being reported erroneously because it happens to be the last symbol in the shared object, and is therefore nothing to do with the SEGV handling.

One possible cause of this kind of crash is that the TLM wrappers have been updated, but some objects have not been recompiled.
We are keen to help diagnose this problem but since we cannot reproduce it, we are not sure what to suggest next.
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GregoryAugier



Joined: 19 Jul 2011
Posts: 6

PostPosted: Thu Aug 11, 2011 9:22 am    Post subject: Reply with quote

Dave,

could you please try with OVPsim instead of CpuManager. This problem is not reproducible using the OVPsim standalone, and I really would like to converge on a resolution of this issue. I'm not convinced by Dunc's explanation about the reason for the crash being a compilation issue. I'm getting similar trace report when using gdb on the standalone simulation, when I do not disable the SEGV handling, however this simulation is working perfectly fine out of gdb.

Thanks

Gregory
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DaveVonBank



Joined: 22 Sep 2008
Posts: 4

PostPosted: Tue Aug 16, 2011 9:25 am    Post subject: Reply with quote

Hi Gregory,

Sorry for the delay in replying. I'm working with Duncan to get this run with OVPsim. We don't have this license feature at Cadence.

Regards,
Dave
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DuncGrah
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Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Wed Aug 17, 2011 4:11 am    Post subject: Reply with quote

Hi Gregory,

I have got a version of Cadences' environment available to me but it is v10.20-v151 so not, unfortunately, the same version you are using v9.20-s038 ..

I'm not yet sure why (change in the SystemC requirements?) but this does not like the OVP 20110427.0 release .. I get the following problem that I have not been able to resolve

Quote:
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
ncelab: *E,SCK512: incorrect use of sc_module_name
In file: sc_module_name.cpp:94.
ncelab: *E,SCK964: Error executing SystemC sc_main() routine
In file: sc_cosim.cpp:788.
ncsc_run: *E,TBELABF: ncelab returned non-zero exit status

I did note your comment about making some code changes, is this problem I am seeing related? If so could you provide details of changes required?

However, I did try this Cadence release with the latest available OVP release 20110721.1 and it does work

Quote:
TOOL: ncsc_run 10.20-v151: (c) Copyright 1995-2010 Cadence Design Systems, Inc.

ncsc_run \
-f run_ovp.f \
+systemc_args+../application/int.elf \
platform.cpp

$CDSROOT = /CADENCE
$TESTDIR = /EXAMPLES/vsp/examples/SystemC_TLM2.0/platform_cpp

TOOL: ncsc 10.20-v151
ncsc C++ parameters:
ncsc -COMPILER $CDSROOT/tools/systemc/gcc/4.4/bin/g++
-f INCA_libs/ncsc_obj/ncsc.args
-MANUAL
-CFLAGS "-DNCSC
-I$CDSROOT/tools/systemc/include_pch
-I$CDSROOT/tools/tbsc/include
-I$CDSROOT/tools/vic/include
-I$CDSROOT/tools/ovm/sc/src
-I$CDSROOT/tools/uvm/uvm_lib/uvm_sc/sc
-I$CDSROOT/tools/uvm/uvm_lib/uvm_ml/sc
-I$CDSROOT/tools/systemc/include/tlm2
-c
-x c++ -Wall
-I$CDSROOT/Imperas.20110721/ImpPublic/include/host
-I$CDSROOT/Imperas.20110721/ImperasLib/source
-DSC_INCLUDE_DYNAMIC_PROCESSES"

ncsc: compiling $/CADENCE/Imperas.20110721/ImperasLib/source/ovpworld.org/modelSupport/tlmPlatform/1.0/tlm2.0/tlmPlatform.cpp

ncsc: compiling $/CADENCE/Imperas.20110721/ImpPublic/source/host/icm/icmCpuManager.cpp

ncsc: compiling $/CADENCE/Imperas.20110721/ImperasLib/source/ovpworld.org/modelSupport/tlmProcessor/1.0/tlm2.0/tlmProcessor.cpp

ncsc: compiling $/CADENCE/Imperas.20110721/ImperasLib/source/ovpworld.org/modelSupport/tlmMMC/1.0/tlm2.0/tlmMmc.cpp

ncsc: compiling $/CADENCE/Imperas.20110721/ImperasLib/source/ovpworld.org/modelSupport/tlmPeripheral/1.0/tlm2.0/tlmPeripheral.cpp

ncsc: compiling $/CADENCE/Imperas.20110721/ImperasLib/source/ovpworld.org/memory/ram/1.0/tlm2.0/tlmMemory.cpp

ncsc: compiling $TESTDIR/platform.cpp

building library ncsc_model.so
ncsc_run: *N,TBNOTOP: No top level specified with -TOP or
-SCTOP. Attempting to use sc_main as the top.

---

ncelab -f INCA_libs/ncsc_obj/simplus.args -f INCA_libs/ncsc_obj/ncelab.args -loadsc libncsc_model -sconly sc_main -snapshot sc_main

ncelab: 10.20-v151: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
Constructing.


OVPsim v20110721.1 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Wed Aug 17 13:06:20 2011


Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110721/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110721/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110721/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.

---

ncsim -f INCA_libs/ncsc_obj/simplus.args -f INCA_libs/ncsc_obj/ncsim.args -loadcfc :cfcbootstrap sc_main

ncsim: 10.20-v151: (c) Copyright 1995-2011 Cadence Design Systems, Inc.

The SystemC(r) Code included in this Product is Copyright 1996 - 2006 by all Contributors. All rights reserved.

The SystemC Code included in this Product has been modified by Cadence Design Systems, Inc. and CoWare, Inc. All such modifications are Copyright (c) 2004-2010 Cadence Design Systems, Inc. and Copyright (c) 2004 CoWare, Inc. All Rights Reserved.

SystemC(r) is a registered trademark of Open SystemC Initiative, Inc. in the United States and other countries and is used with permission.

Constructing.


OVPsim v20110721.1 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Wed Aug 17 13:06:21 2011


Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110721/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110721/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/CADENCE/Imperas.20110721/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.
Info (16450) /top.uart1: main done
ncsim> run
TEST: main starts
TEST: Initialise:
TEST: Enable UART:
Interrupt Handler 0x02 (1)
Character sent
TEST: main send string
TEST: Send String: Hello World
... snip ...
TEST: main done
SystemC: simulation stopped by user.


SC simulation stopped by user.

SystemC : SystemC stopped at time 9223372036853727
ncsim> exit
Finished sc_main.
Info
... snip ...

OVPsim finished: Wed Aug 17 13:06:22 2011
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim v20110721.1 Open Virtual Platform simulator from www.OVPworld.org.



I'll see if I can get hold of the older version of Cadence tools to try again to reproduce the problem with OVP 20110427.0

I'm also trying to get an OVPsim license to Dave at Cadence.
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DuncGrah
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Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Wed Aug 17, 2011 7:39 am    Post subject: Reply with quote

Could you please try the latest version of OVPsim (currently 20110721.0) and let me know how you get on.

I know there were some changes in some of the SystemC files supplied.
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DaveVonBank



Joined: 22 Sep 2008
Posts: 4

PostPosted: Thu Aug 18, 2011 7:15 am    Post subject: Results Running OVPsim v20110427.0 with nc 09.20-s038 Reply with quote

Hi Gregory / Duncan:

I just successfully ran the example with the combination of platforms and software versions that I believe Gregory is using. The results are pasted below. Note that the 20110427.0 OVP release that I used had some changes in 3 files:

Imperas.20110427ImperasLib/source/ovpworld.org/modelSupport/tlmProcessor/1.0/tlm2.0/tlmProcessor.hpp
Imperas.20110427ImperasLib/source/ovpworld.org/modelSupport/tlmProcessor/1.0/tlm2.0/tlmProcessor.cpp
Imperas.20110427ImperasLib/source/ovpworld.org/modelSupport/tlmPeripheral/1.0/tlm2.0/tlmPeripheral.cpp

These were to get around errors and warnings in the SystemC/TLM2.0 code. Gregory, I believe you indicated you made changes like these also. In any case, these changes were all incorporated into the 20110721.1 release so if you advance to that release they are not necessary. If you need to use the 20110427 release for some reason, Duncan can provide these files.

Regards,
Dave

Here are the results:

oak[108]9.20_OVPsim_platform_cpp > uname -a
Linux oak 2.6.9-78.0.25.ELsmp #1 SMP Fri Jun 26 07:40:54 EDT 2009 x86_64 x86_64 x86_64 GNU/Linux
################################ Compile/Link #################################
ncsc_run -stop link -f run_ovp.f +systemc_args+../application/int.elf platform.cpp
TOOL: ncsc_run 09.20-s038: (c) Copyright 1995-2009 Cadence Design Systems, Inc.

ncsc_run \
-stop link \
-f run_ovp.f \
+systemc_args+../application/int.elf \
platform.cpp

$CDSROOT = /grid/avs/install/ius/9.2/09.20.038-s
$TESTDIR = /dv/scratch/users/vonbank/installations/ovp/Examples_20110427/Platforms/SystemC_TLM2.0/9.20_OVPsim_platform_cpp

TOOL: ncsc 09.20-s038
ncsc C++ parameters:
ncsc -COMPILER $CDSROOT/tools/systemc/gcc/4.1/bin/g++
-f INCA_libs/ncsc_obj/ncsc.args
-MANUAL
-CFLAGS "-DNCSC
-I$CDSROOT/tools/systemc/include_pch
-I$CDSROOT/tools/tbsc/include
-I$CDSROOT/tools/vic/include
-I$CDSROOT/tools/ovm/sc/src
-I$CDSROOT/tools/systemc/include/tlm2
-c
-x c++ -Wall
-I/home/vonbank/ovp/Imperas.20110427/ImpPublic/include/host
-I/home/vonbank/ovp/Imperas.20110427/ImperasLib/source
-DSC_INCLUDE_DYNAMIC_PROCESSES"

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmPlatform/1.0/tlm2.0/tlmPlatform.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImpPublic/source/host/icm/icmCpuManager.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmProcessor/1.0/tlm2.0/tlmProcessor.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmMMC/1.0/tlm2.0/tlmMmc.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmPeripheral/1.0/tlm2.0/tlmPeripheral.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/memory/ram/1.0/tlm2.0/tlmMemory.cpp

ncsc: compiling $TESTDIR/platform.cpp
$CDSROOT/tools/systemc/include/tlm2/tlm_h/tlm_2_interfaces/tlm_fw_bw_ifs_transmitter.h:151: warning: unusedvariable 'recording'

building library ncsc_model.so
ncsc_run: *N,TBLINK: Stopping after link due to -STOP LINK option.
All libraries and executables are linked.

################################# Elaborate ###################################
oak[100]9.20_OVPsim_platform_cpp > !78
ncelab -loadsc ./libncsc_model.so sc_main +systemc_args+../application/int.elf
ncelab: 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
Constructing.


OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Thu Aug 18 10:45:30 2011


Warning (LIC_EXP) License feature 'IMP_OVPSIM' will expire in 13 days
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.

################################# Simulate ####################################
oak[101]9.20_OVPsim_platform_cpp > !79
ncsim sc_main +systemc_args+../application/int.elf
ncsim: 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.

The SystemC(r) Code included in this Product is Copyright 1996 - 2006 by all Contributors. All rights reserved.

The SystemC Code included in this Product has been modified by Cadence Design Systems, Inc. and CoWare, Inc. All such modifications are Copyright (c) 2004-2010 Cadence Design Systems, Inc. and Copyright (c) 2004 CoWare, Inc. All Rights Reserved.

SystemC(r) is a registered trademark of Open SystemC Initiative, Inc. in the United States and other countries and is used with permission.

Constructing.


OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Thu Aug 18 10:46:09 2011


Warning (LIC_EXP) License feature 'IMP_OVPSIM' will expire in 13 days
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.
Info (16450) /uart1: main done
ncsim> run
TEST: main starts
TEST: Initialise:
TEST: Enable UART:
Interrupt Handler 0x02 (1)
Character sent
TEST: main send string
TEST: Send String: Hello World

Send char H (0x48)
Interrupt Handler 0x02 (2)
Character sent
Send char e (0x65)
Interrupt Handler 0x02 (3)
Character sent
Send char l (0x6c)
Interrupt Handler 0x02 (4)
Character sent
Send char l (0x6c)
Interrupt Handler 0x02 (5)
Character sent
Send char o (0x6f)
Interrupt Handler 0x02 (6)
Character sent
Send char (0x20)
Interrupt Handler 0x02 (7)
Character sent
Send char W (0x57)
Interrupt Handler 0x02 (8)
Character sent
Send char o (0x6f)
Interrupt Handler 0x02 (9)
Character sent
Send char r (0x72)
Interrupt Handler 0x02 (10)
Character sent
Send char l (0x6c)
Interrupt Handler 0x02 (11)
Character sent
Send char d (0x64)
Interrupt Handler 0x02 (12)
Character sent
Send char
(0x0a)
Interrupt Handler 0x02 (13)
Character sent
TEST: main done
SystemC: simulation stopped by user.


SC simulation stopped by user.

SystemC : SystemC stopped at time 9223372036853727
ncsim> exit
Finished sc_main.
Info
Info ---------------------------------------------------
Info PSE SIMULATION TIME STATISTICS
Info 0.01 seconds: PSE 'uart1' (and 1 terminated thread, 39 terminated callbacks)
Info ---------------------------------------------------
Info
Info ---------------------------------------------------
Info CPU '/cpu1' STATISTICS
Info Type : or1k
Info Nominal MIPS : 100
Info Final program counter : 0x138
Info Simulated instructions: 77,991
Info Simulated MIPS : 0.1
Info ---------------------------------------------------
Info
Info ---------------------------------------------------
Info SIMULATION TIME STATISTICS
Info Simulated time : 0.78 seconds
Info User time : 0.02 seconds
Info System time : 0.00 seconds
Info Elapsed time : 0.82 seconds
Info Host utilization : 13.0% (wallclock enabled)
Info ---------------------------------------------------


OVPsim finished: Thu Aug 18 10:46:10 2011
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.

################################# All Steps ####################################

rm -rf INCA_libs
oak[105]9.20_OVPsim_platform_cpp > !80
ncsc_run -f run_ovp.f +systemc_args+../application/int.elf platform.cpp
TOOL: ncsc_run 09.20-s038: (c) Copyright 1995-2009 Cadence Design Systems, Inc.

ncsc_run \
-f run_ovp.f \
+systemc_args+../application/int.elf \
platform.cpp

$CDSROOT = /grid/avs/install/ius/9.2/09.20.038-s
$TESTDIR = /dv/scratch/users/vonbank/installations/ovp/Examples_20110427/Platforms/SystemC_TLM2.0/9.20_OVPsim_platform_cpp

TOOL: ncsc 09.20-s038
ncsc C++ parameters:
ncsc -COMPILER $CDSROOT/tools/systemc/gcc/4.1/bin/g++
-f INCA_libs/ncsc_obj/ncsc.args
-MANUAL
-CFLAGS "-DNCSC
-I$CDSROOT/tools/systemc/include_pch
-I$CDSROOT/tools/tbsc/include
-I$CDSROOT/tools/vic/include
-I$CDSROOT/tools/ovm/sc/src
-I$CDSROOT/tools/systemc/include/tlm2
-c
-x c++ -Wall
-I/home/vonbank/ovp/Imperas.20110427/ImpPublic/include/host
-I/home/vonbank/ovp/Imperas.20110427/ImperasLib/source
-DSC_INCLUDE_DYNAMIC_PROCESSES"

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmPlatform/1.0/tlm2.0/tlmPlatform.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImpPublic/source/host/icm/icmCpuManager.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmProcessor/1.0/tlm2.0/tlmProcessor.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmMMC/1.0/tlm2.0/tlmMmc.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/modelSupport/tlmPeripheral/1.0/tlm2.0/tlmPeripheral.cpp

ncsc: compiling $/home/vonbank/ovp/Imperas.20110427/ImperasLib/source/ovpworld.org/memory/ram/1.0/tlm2.0/tlmMemory.cpp

ncsc: compiling $TESTDIR/platform.cpp
$CDSROOT/tools/systemc/include/tlm2/tlm_h/tlm_2_interfaces/tlm_fw_bw_ifs_transmitter.h:151: warning: unusedvariable 'recording'

building library ncsc_model.so
ncsc_run: *N,TBNOTOP: No top level specified with -TOP or
-SCTOP. Attempting to use sc_main as the top.

---

ncelab -f INCA_libs/ncsc_obj/simplus.args -f INCA_libs/ncsc_obj/ncelab.args -loadsc libncsc_model -sconly sc_main -snapshot sc_main

ncelab: 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
Constructing.


OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Thu Aug 18 10:52:21 2011


Warning (LIC_EXP) License feature 'IMP_OVPSIM' will expire in 13 days
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.

---

ncsim -f INCA_libs/ncsc_obj/simplus.args -f INCA_libs/ncsc_obj/ncsim.args -loadcfc :cfcbootstrap sc_main

ncsim: 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.

The SystemC(r) Code included in this Product is Copyright 1996 - 2006 by all Contributors. All rights reserved.

The SystemC Code included in this Product has been modified by Cadence Design Systems, Inc. and CoWare, Inc. All such modifications are Copyright (c) 2004-2010 Cadence Design Systems, Inc. and Copyright (c) 2004 CoWare, Inc. All Rights Reserved.

SystemC(r) is a registered trademark of Open SystemC Initiative, Inc. in the United States and other countries and is used with permission.

Constructing.


OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
Copyright (c) 2005-2011 Imperas Software Ltd. Contains Imperas Proprietary Information.
Licensed Software, All Rights Reserved.
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim started: Thu Aug 18 10:52:23 2011


Warning (LIC_EXP) License feature 'IMP_OVPSIM' will expire in 13 days
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/semihosting/or1kNewlib/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/ovpworld.org/processor/or1k/1.0/model.so'
Info (ICM_AL) Found attribute symbol 'modelAttrs' in file '/dv/scratch/users/vonbank/installations/ovp/Imperas.20110427/lib/Linux/ImperasLib/national.ovpworld.org/peripheral/16450/1.0/model.so'
Using SystemC TLM2.0 Memory with DMI
Info (OR_OF) Target 'ram1' has object file read from '../application/int.elf'
Info (OR_SH) Section flg sect addr size load addr file offset
Info (OR_SD) .text -ax 0x00000000 0x0000cab0 0x00000000 0x00002000
Info (OR_SD) .rodata -a- 0x0000cab0 0x00000520 0x0000cab0 0x0000eab0
Info (OR_SD) .data wa- 0x0000efd0 0x00000868 0x0000efd0 0x0000efd0
Starting sc_main.
Info (16450) /uart1: main done
ncsim> run
TEST: main starts
TEST: Initialise:
TEST: Enable UART:
Interrupt Handler 0x02 (1)
Character sent
TEST: main send string
TEST: Send String: Hello World

Send char H (0x48)
Interrupt Handler 0x02 (2)
Character sent
Send char e (0x65)
Interrupt Handler 0x02 (3)
Character sent
Send char l (0x6c)
Interrupt Handler 0x02 (4)
Character sent
Send char l (0x6c)
Interrupt Handler 0x02 (5)
Character sent
Send char o (0x6f)
Interrupt Handler 0x02 (6)
Character sent
Send char (0x20)
Interrupt Handler 0x02 (7)
Character sent
Send char W (0x57)
Interrupt Handler 0x02 (8)
Character sent
Send char o (0x6f)
Interrupt Handler 0x02 (9)
Character sent
Send char r (0x72)
Interrupt Handler 0x02 (10)
Character sent
Send char l (0x6c)
Interrupt Handler 0x02 (11)
Character sent
Send char d (0x64)
Interrupt Handler 0x02 (12)
Character sent
Send char
(0x0a)
Interrupt Handler 0x02 (13)
Character sent
TEST: main done
SystemC: simulation stopped by user.


SC simulation stopped by user.

SystemC : SystemC stopped at time 9223372036853727
ncsim> exit
Finished sc_main.
Info
Info ---------------------------------------------------
Info PSE SIMULATION TIME STATISTICS
Info 0.01 seconds: PSE 'uart1' (and 1 terminated thread, 39 terminated callbacks)
Info ---------------------------------------------------
Info
Info ---------------------------------------------------
Info CPU '/cpu1' STATISTICS
Info Type : or1k
Info Nominal MIPS : 100
Info Final program counter : 0x138
Info Simulated instructions: 77,991
Info Simulated MIPS : 0.1
Info ---------------------------------------------------
Info
Info ---------------------------------------------------
Info SIMULATION TIME STATISTICS
Info Simulated time : 0.78 seconds
Info User time : 0.03 seconds
Info System time : 0.00 seconds
Info Elapsed time : 0.74 seconds
Info Host utilization : 4.3% (wallclock enabled)
Info ---------------------------------------------------


OVPsim finished: Thu Aug 18 10:52:23 2011
Visit www.imperas.com for multicore debug, verification and analysis solutions.
OVPsim v20110427.0 Open Virtual Platform simulator from www.OVPworld.org.
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DuncGrah
OVP Technologist
OVP Technologist


Joined: 27 Feb 2008
Posts: 1656
Location: United Kingdom

PostPosted: Mon Aug 22, 2011 1:38 am    Post subject: Reply with quote

Hi Gregory

Please let me know if the update worked for you?

We believe we've got a good integration working with Cadence and OVP, we'd like to know if you have experienced this as well.

Thanks

Duncan
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