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13 August 2012 - 12:00am — Video

Video Link: Imperas and Cadence Discussion


Hear from Larry Lapides, Vice President of Sales at Imperas, and Larry Melling Product Manager - Virtual System Platform at Cadence, as they describe the collaboration and use of the Cadence Virtual System Platform along with Imperas processor models and verification analysis and profiling tools to address challenges of embedded software development for complex SOCs.

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In the News

-- The Lost Art Of Processor Verification
-- Speeding Up AI With Vector Instructions
---- More (73) ----

Press Releases

-- Imperas releases new RISC-V Processor Verification IP to drive RISC-V adoption forward with a flexible methodology for all SoC adopters
-- Silicon Labs selects Imperas RISC-V Reference Model for verification
---- More (113) ----

Views and Blogs

-- The Lost Art Of Processor Verification
-- RISC-V Verification Challenges Spread
---- More (66) ----

Industry Events

-- Imperas at 3rd Annual RISC-V Summit, December 8-10 2020
-- Imperas on OpenHW TV episode #5 - Update on Processor Verification, October 29 2020
---- More (88) ----

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