Imperas at 3rd Annual RISC-V Summit, December 8-10 2020

Imperas supporting the online virtual event with the latest updates for RISC-V Processor Verification and Architecture Exploration for AI with virtual platforms.

RISC-V Summit 2020

 

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation at the RISC-V International 3rd Annual RISC-V Summit 2020 including talks and virtual demonstrations and live Q&A discussions with the Imperas team.

 

Presentation ‘Getting Started with RISC-V Verification what’s next after compliance testing'

  • Speaker:         Lee Moore – Imperas Software
  • Co-Author:     Simon Davidmann – Imperas Software
  • When:             TBD

Abstract: Historically for SoC design based on established processor IP cores the project time and cost estimates for verification range from 60-80%, which does not include the verification work performed by the IP provider. With the design freedoms of RISC-V all SoC adopters will have the options and flexibility to develop a custom processor targeted at just the right optimized solution. The design challenge is to explore these freedoms efficiency and quickly select the optional configuration. 
The RISC-V processor design verification (DV) task needs to overlap both the design exploration phase and also the SoC development and test work. This is essential when custom extensions are utilized for lightweight inter-processor communications, as the DV of the processor and SoC DV becomes interdependent.
Using SystemVerilog UVM test benches with an encapsulated RISC-V reference model helps support a step-and-compare methodology. This tutorial highlights the experience with both identifying potential issues and also the flows for analysis, resolution and ultimately coverage driven metrics for DV plan progress. One of the key requirements for the ecosystem to develop the efficiencies of scale across all implementations is the use and adoption of the RISC-V compliance suite by all developers. The latest test status and details on the distinction between the coverage of the compliance suite and a full DV test plan will be outlined. This talk highlights the results found testing some popular open source cores and outlines the methods to help address the DV phase of your next project.

 

Presentation ‘Virtual platforms for AI and ML architecture exploration’

  • Speaker:         Simon Davidmann – Imperas Software
  • When:             TBD

Abstract: RISC-V is gaining traction for AI and Machine Learning applications as system designers migrate cloud-based algorithms to dedicated hardware. RISC-V offers the options to fine tune the processor features and configure vector engines to accelerate the key functions. In many core arrays the processors can be a mix of capabilities for a true heterogeneous solution. The RISC-V support of custom instruction and extension can be used for both new functions and also lightweight inter-processor communications across the arrays of processors. 
Using virtual platforms allows system designers to explore various configurations and arrangements of processors and test these with the full application workloads and real-world datasets. Given the broad range of target markets looking at AI solutions, RISC-V is uniquely positioned to scale across all the compute requirements.
As the front end of the design exploration moves towards the detailed design phase the reference model approach allows the hardware developers to use a functional model as part of the design specification and help develop the test bench with behavioral models. Developing software before silicon is useful for the internal project teams, but in many markets the option to provide early evaluation platforms to prospects and partners is a key way to develop support and interest for these new devices.
Based on experience with advanced AI designs this talk with highlight the virtual platforms role in these new market segments with multi-processor design techniques illustrated with examples of current design projects.

 

For more information, or to set up virtual meetings with Imperas team during the RISC-V Summit, please contact info@imperas.com.

 

About the RISC-V Summit 2020
For more information see https://tmt.knect365.com/risc-v-summit/
 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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