Imperas demonstrations include RISC-V Processor Reference Models for hardware verification and the first commercial simulator for RISC-V Vector Extensions
Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, is pleased to be a contributing sponsor for the second annual RISC-V Summit in December in San Jose, California. Imperas will exhibit RISC-V Processor Reference Models for hardware verification and the first commercial simulator for RISC-V Vector Extensions, and RISC-V custom instruction design flows. Imperas conference presentations will focus on RISC-V Processor verification and RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays.
Please contact info@imperas.com to set up a meeting at the RISC-V Summit 2019, or to learn more about Imperas virtual prototyping solutions for embedded software development, debug and test.
Register for an Expo or Conference Pass Now with Special Discount Promotion!
Register for the Free Expo-only pass at this link. Or click here to register for the keynotes, conference or tutorial with 15% discount, select the ticket option and press ‘add to basket’ button then enter the VIP code: Imperas.
Presentation: Avoiding Amdahl's Law: RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays
Presentation: RISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies
Tutorial: RISC-V Verification for Processor Cores and Optional Custom Extensions
Exhibit: Stop by the Imperas booth #416 and see all the latest demonstrations and virtual platform technology for RISC-V based designs, including Verification and custom instruction, plus support for the latest RISC-V specifications for Vectors and Bit Manipulation. For more information, or to set up meetings with Imperas at the RISC-V Summit 2019, please contact info@imperas.com.
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