Imperas on OpenHW TV – Verification of CORE-V open source RISC-V processor IP cores using Imperas RISC-V reference model.
Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation in the 5th episode of OpenHW TV focused on the updates for Verification of CORE-V open source RISC-V processor IP cores. Guests include the Co-Chairs of the OpenHW verification task group (Futurewei and SiliconLabs) with contributing members Imperas and Metrics highlighting the open source CORE-V processor IP Design Verification (DV) plan using state of the art flows and SystemVerilog UVM testbenches with encapsulated Imperas RISC-V reference model, coverage based flow, and Metrics flexible cloud based environment.
Following the updates and presentations by Imperas and Metrics all the panellist will be available for the live Q&A session with audience participation.
Registration is now open at this link.
About Imperas
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
All trademarks or registered trademarks are the property of their respective holders.
# # #