Imperas presenting at Cadence Live Silicon Valley, April 19-20 2023
Imperas Demonstrates Virtual Platforms and RISC-V Models for Hardware-Software Co-Verification
Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced their participation at the Cadence Live Silicon Valley event, April 19-20 2023, at the Santa Clara Convention Center. Cadence LIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. Imperas will present a technical paper on Fast Processor Models for Software Bring Up and Hardware-Software Co-Verification.
Presentation: RISC-V Fast Processor Models for Software Bring Up and Hardware-Software Co-Verification with Palladium
Abstract:
The RISC-V instruction set architecture (ISA) open standard has accelerating momentum in the semiconductor community. Adopters include both traditional semiconductor companies and also vertically integrated systems companies building their own SoCs. This momentum is due to the open nature of the ISA, enabling users to build domain specific processors that can help to differentiate SoCs and end products. This flexibility is a double-edged sword. Unlike traditional processor IP, custom instructions are routinely added to RISC-V processors. This means that the ecosystem - both hardware and software tools - needs to be adaptable to these custom instructions.
Key to the success of RISC-V is the ecosystem of support available for software development and processor verification. As adopters explore the new design freedoms of RISC-V this has implications affecting software porting, development and bring up, plus the new requirements for RISC-V processor design verification. Software simulation coupled with hardware emulation addresses both these areas, providing a methodology for software development, whether porting software or new development, and for processor verification through hardware-software co-verification.
This paper reports on the use of Open Virtual Platforms (OVP) Fast Processor Models for this hybrid simulation-emulation technique. Custom instructions and other custom features of RISC-V processors are discussed, and the modelling architecture and development methodology for achieving high quality, high performance (~500 million instructions per second) processor models is presented. The processor models are integrated with the Helium SystemC simulator, enabling the hybrid simulation-emulation usage with Palladium. When used in this hybrid methodology, for example booting Linux in the processor model simulation then transferring execution to the emulator, performance improvements of over 100x can be achieved versus standalone emulation.
While this flow has already been deployed with Palladium users, the advantage of adopting the same interface to Protium means that the FPGA prototyping tool can now also be used in this hybrid mode.
This paper will also present a customer use case involving the development of a SoC for AI/ML with approximately 150 RISC-V cores, highlighting how hybrid simulation-emulation is critical to the success of this RISC-V based SoC.
Presenter: Larry Lapides, Imperas Software
Co-Authors: Andrew Wilmot and Ross Dickson, Cadence Design Systems
When: Verification Track - April 20, 2023, AM Sessions
For more information, or to set up meetings with the Imperas team at Cadence Live Silicon Valley, please email info@imperas.com
About Cadence Live Silicon Valley 2023
When: April 19-20, 2023
Where: Santa Clara Convention Center, California, USA
Event info: For more details, please visit this link.
About Imperas
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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