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OVP RISC-V Solutions

Open Virtual Platforms (OVP) provides open source models of RISC-V processors, cores, modules, and platforms. OVP also makes available a fully supported closed source simulator, OVPsim that is free for non-commercial usage to execute these models.

Imperas provides a commercially supported, full set of simulators, debuggers and tools to use with the OVP models and platforms.

Information about OVP and RISC-V

For information on the background of OVP visit the introductory, home, about, and technology sections of the OVP site.
For information on all the available models available visit the models and library pages.
For support information visit the user forum.

RISC-V models available

The following pages provide information on the OVP support for the RISC-V processor architecture and silicon.

OVPsim RISC-V Simulator

The OVP simulator allows you to simulate the prebuilt platforms and models form the library while also allowing you to create your own models. Read more about OVPsim here: https://www.ovpworld.org/technology_ovpsim.

Free riscvOVPsim RISC-V Simulators

There are two free riscvOVPsim simulators available:

riscvOVPsim available from github.com/riscv-ovpsim is for running simple tests and the RISC-V compliance suite.

riscvOVPsimPlus available from www.ovpworld.org/riscv-ovpsim-plus is for test development and verification.

OVP Debuggers for RISC-V software debug

The OVP simulators are designed to work with GDB-like debuggers. OVPsim is fully supported working with GDB for single core debugging and the Imperas Multi Processor Debugger when your design has multi-core or many-core processor instances.

OVPsim comes with a debug GUI from Imperas called iGui to provide a graphical debug experience for RISC-V processors when using GDB with the OVP simulator.

If you are used to using Eclipse/CDT, then OVPsim is also configured to work with that.

You can also use the Imperas Multi Processor Debugger with the Imperas eGui Eclipse based GUI. For more information visit www.imperas.com.

Videos showing RISC-V simulation and debug

There are several video on the use of RISC-V ISA and core models with the OVP simulation and debug solutions.
Please have a look at: https://www.ovpworld.org/demosandvideos where you will find videos showing very fast simulation on bare metal, operating systems running like Linux and FreeRTOS, and multi-core debug across RISC-V based platforms.