MIPS Technologies is a leading provider of industry-standard processor architectures and cores that power some of the world's most popular products for the home entertainment, communications, networking and portable multimedia markets.

For more than two decades, MIPS Technologies has been a leader and innovator in the worldwide embedded semiconductor market. At the heart of MIPS is its architecture, developed 20 years ago by Stanford University engineering Professor John Hennessy-now president of Stanford University. Hennessy took the lead in RISC processing and created an elegant, streamlined architecture with a scalability that has met the demands of generations of applications, preserving the wealth of development tools and software that support them. Today, the MIPS architecture is an industry standard and the performance leader within the embedded industry

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MIPS Processor Families

MIPS Technologies offers the industry's broadest array of low power, high-performance embedded microprocessor cores that power hundreds of millions of products around the globe. The company develops processor cores targeted for every unique design need, from entry-level to some of the industry's highest performing cores. MIPS targets high-growth markets that are paving the way for next-generation embedded designs, including digital consumer and a growing presence in mobile applications, broadband access and networking, and state-of-the-art communications.

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The MIPS Aptiv range is a new generation of processor cores offering a high level of performance and efficiency for applications across the home entertainment, networking, mobile and embedded segments.
The high-performance proAptiv core achieves the highest CoreMark/MHz score reported for any licensable IP core, together with leading silicon efficiency.
The interAptiv leverages a balanced nine-stage pipeline with multi-threading to deliver leading performance efficiency. Ideal for highly-parallel applications requiring cost and power optimization, such as smart gateways, baseband processing in LTE user equipment and small cells, SSD controllers and automotive equipment.
The microAptiv core with microMIPS code compression instruction set architecture integrates DSP and SIMD functionality to address signal processing requirements for a wide range of microcontroller and entry-level embedded segments including industrial control, smart meters, automotive and wired/wireless communications.

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The MIPS Warrior generation of cores includes 32-bit and 64-bit variants with a focus on superior performance efficiency across the high-end, mid-range and entry-level/microcontroller CPUs. Building on the true 32-bit and 64-bit instruction set compatibility of MIPS, Warrior cores provide binary compatibility from the entry-level to the high-end.

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