OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW Group provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

There are a range of cores, known as CORE-V with the initial one being the 32 bit CV32E40P originally known as the PULP RI5CY core (from ETH Zurich university). The CORE-V CV32E40P is a 32bit, 4-stage core that implements, RV32IMFCXpulp, has an optional 32-bit FPU supporting the F extension and instruction set extensions for DSP operations, including hardware loops, SIMD extensions, bit manipulation and post-increment instructions. The CV32E40P has been extensively verified against the Imperas OVP golden reference model.

Information on OVP models of OpenHW Group CORE-V RISC-V range of processors

More on OpenHwGroup processor families