Berkeley's RISC-V (pronounced 'risk-five') is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now becoming a standard open architecture for industry implementations under the governance of the RISC-V Foundation.

The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

In contrast to most ISAs, the RISC-V ISA can be freely used for all types of use, permitting anyone to design, manufacture and sell RISC-V chips and software.

While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency.

The instruction set also has a substantial body of supporting software, which fixes a usual weakness of new instruction sets.

More information on OVP models of 32bit RISC-V processors

More information on OVP models of 64bit RISC-V processors

More on RISC-V processor families