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AE350



OVP Virtual Platform: AE350

This page provides detailed information about the OVP Virtual Platform Model of the andes.ovpworld.org AE350 platform.

Licensing

Open Source Apache 2.0

Description

Andes AE350 module (skeleton)

Reference

Andes BSP v5.0 ae350 BSP Definition

Limitations

This is a skeleton platform that contains only those peripherals required to boot FreeRTOS demo.

Location

The AE350 virtual platform is located in an Imperas/OVP installation at the VLNV: andes.ovpworld.org / module / AE350 / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorcpu0andes.ovpworld.orgriscvNX25
PeripheralBMCovpworld.orgtrap
PeripheralAHBDECovpworld.orgtrap
PeripheralMACovpworld.orgtrap
PeripheralLCDCovpworld.orgtrap
PeripheralSMCovpworld.orgtrap
PeripheralPLICovpworld.orgtrap
PeripheralPLMTandes.ovpworld.orgNCEPLMT100
PeripheralPLIC_SWovpworld.orgtrap
PeripheralPLDMovpworld.orgtrap
PeripheralAPBBRGovpworld.orgtrap
PeripheralSMUovpworld.orgtrap
PeripheralUART1andes.ovpworld.orgATCUART100
PeripheralUART2andes.ovpworld.orgATCUART100
PeripheralPITovpworld.orgtrap
PeripheralWDTovpworld.orgtrap
PeripheralRTCovpworld.orgtrap
PeripheralGPIOovpworld.orgtrap
PeripheralI2Covpworld.orgtrap
PeripheralSPI1ovpworld.orgtrap
PeripheralDMACovpworld.orgtrap
PeripheralAC97ovpworld.orgtrap
PeripheralSDCovpworld.orgtrap
PeripheralSPI2ovpworld.orgtrap
Memoryeilmovpworld.orgram
Memoryedlmovpworld.orgram
Memoryspimemovpworld.orgram
Memorystackovpworld.orgram
Busbus0(builtin)address width:buswidth

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [andes.ovpworld.org/processor/riscv/1.0] instance: cpu0

Processor model type: 'riscv' variant 'NX25' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/andes.ovpworld.org/processor/riscv/1.0/doc
- the OVP website: OVP_Model_Specific_Information_andes_riscv_NX25.pdf

Description

RISC-V NX25 64-bit processor model

Licensing

This Model is released under the Open Source Apache 2.0

Extensions

The model has the following architectural extensions enabled, and the following bits in the misa CSR Extensions field will be set upon reset:
misa bit 0: extension A (atomic instructions)
misa bit 2: extension C (compressed instructions)
misa bit 8: RV32I/64I/128I base ISA
misa bit 12: extension M (integer multiply/divide instructions)
misa bit 20: extension U (User mode)
misa bit 23: extension X (non-standard extensions present)
To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register.
Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any value defined in the base variant.
Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any value defined in the base variant.

Available (But Not Enabled) Extensions

The following extensions are supported by the model, but not enabled by default in this variant:
misa bit 1: extension B (bit manipulation extension) (NOT ENABLED)
misa bit 3: extension D (double-precision floating point) (NOT ENABLED)
misa bit 4: RV32E base ISA (NOT ENABLED)
misa bit 5: extension F (single-precision floating point) (NOT ENABLED)
misa bit 13: extension N (user-level interrupts) (NOT ENABLED)
misa bit 18: extension S (Supervisor mode) (NOT ENABLED)
misa bit 21: extension V (vector extension) (NOT ENABLED)
To add features from this list to the base variant, use parameter "add_Extensions". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are absent.

General Features

On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
Values written to "mtvec" are masked using the value 0xfffffffffffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required.
On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required.
WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
Unaligned memory accesses are not supported for AMO instructions by this variant. Set parameter "unalignedAMO" to "T" to enable such accesses.
A PMP unit is not implemented by this variant. Set parameter "PMP_registers" to indicate that the unit should be implemented with that number of PMP entries.
LR/SC instructions are implemented with a 1-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".

CLIC

The model can be configured to implement a Core Local Interrupt Controller (CLIC) using parameter "CLICLEVELS"; when non-zero, the CLIC is present with the specified number of interrupt levels (2-256), as described in the RISC-V Core-Local Interrupt Controller specification (see references). When "CLICLEVELS" is non-zero, further parameters are made available to configure other aspects of the CLIC, as described below.
The model can configured either to use an internal CLIC model (if parameter "externalCLIC" is False) or to present a net interface to allow the CLIC to be implemented externally in a platform component (if parameter "externalCLIC" is True). When the CLIC is implemented internally, net ports for standard interrupts and additional local interrupts are available. When the CLIC is implemented externally, a net port interface allowing the highest-priority pending interrupt to be delivered is instead present. This is described below.

CLIC Common Parameters

This section describes parameters applicable whether the CLIC is implemented internally or externally. These are:
"CLICANDBASIC": this Boolean parameter indicates whether both CLIC and basic interrupt controller are present (if True) or whether only the CLIC is present (if False).
"CLICXNXTI": this Boolean parameter indicates whether xnxti CSRs are implemented (if True) or unimplemented (if False).
"CLICXCSW": this Boolean parameter indicates whether xscratchcsw and xscratchcswl CSRs registers are implemented (if True) or unimplemented (if False).
"mclicbase": this parameter specifies the CLIC base address in physical memory.
"tvt_undefined": this Boolean parameter indicates whether xtvt CSRs registers are implemented (if True) or unimplemented (if False). If the registers are unimplemented then the model will use basic mode vectored interrupt semantics based on the xtvec CSRs instead of Selective Hardware Vectoring semantics described in the specification.
"intthresh_undefined": this Boolean parameter indicates whether xintthresh CSRs registers are implemented (if True) or unimplemented (if False).
"mclicbase_undefined": this Boolean parameter indicates whether the mclicbase CSR register is implemented (if True) or unimplemented (if False).

CLIC Internal-Implementation Parameters

This section describes parameters applicable only when the CLIC is implemented internally. These are:
"CLICCFGMBITS": this Uns32 parameter indicates the number of bits implemented in cliccfg.nmbits, and also indirectly defines CLICPRIVMODES. For cores which implement only Machine mode, or which implement Machine and User modes but not the N extension, the parameter is absent ("CLICCFGMBITS" must be zero in these cases).
"CLICCFGLBITS": this Uns32 parameter indicates the number of bits implemented in cliccfg.nlbits.
"CLICSELHVEC": this Boolean parameter indicates whether Selective Hardware Vectoring is supported (if True) or unsupported (if False).

CLIC External-Implementation Net Port Interface

When the CLIC is externally implemented, net ports are present allowing the external CLIC model to supply the highest-priority pending interrupt and to be notified when interrupts are handled. These are:
"irq_id_i": this input should be written with the id of the highest-priority pending interrupt.
"irq_lev_i": this input should be written with the highest-priority interrupt level.
"irq_sec_i": this 2-bit input should be written with the highest-priority interrupt security state (00:User, 01:Supervisor, 11:Machine).
"irq_shv_i": this input port should be written to indicate whether the highest-priority interrupt should be direct (0) or vectored (1). If the "tvt_undefined parameter" is False, vectored interrupts will use selective hardware vectoring, as described in the CLIC specification. If "tvt_undefined" is True, vectored interrupts will behave like basic mode vectored interrupts.
"irq_id_i": this input should be written with the id of the highest-priority pending interrupt.
"irq_i": this input should be written with 1 to indicate that the external CLIC is presenting an interrupt, or 0 if no interrupt is being presented.
"irq_ack_o": this output is written by the model on entry to the interrupt handler (i.e. when the interrupt is taken). It will be written as an instantaneous pulse (i.e. written to 1, then immediately 0).
"irq_id_o": this output is written by the model with the id of the interrupt currently being handled. It is valid during the instantaneous irq_ack_o pulse.
"sec_lvl_o": this output signal indicates the current secure status of the processor, as a 2-bit value (00=User, 01:Supervisor, 11=Machine).

Load-Reserved/Store-Conditional Locking

By default, LR/SC locking is implemented automatically by the model and simulator, with a reservation granule defined by the "lr_sc_grain" parameter. It is also possible to implement locking externally to the model in a platform component, using the "LR_address", "SC_address" and "SC_valid" net ports, as described below.
The "LR_address" output net port is written by the model with the address used by a load-reserved instruction as it executes. This port should be connected as an input to the external lock management component, which should record the address, and also that an LR/SC transaction is active.
The "SC_address" output net port is written by the model with the address used by a store-conditional instruction as it executes. This should be connected as an input to the external lock management component, which should compare the address with the previously-recorded load-reserved address, and determine from this (and other implementation-specific constraints) whether the store should succeed. It should then immediately write the Boolean success/fail code to the "SC_valid" input net port of the model. Finally, it should update state to indicate that an LR/SC transaction is no longer active.
It is also possible to write zero to the "SC_valid" input net port at any time outside the context of a store-conditional instruction, which will mark any active LR/SC transaction as invalid.
Irrespective of whether LR/SC locking is implemented internally or externally, taking any exception or interrupt or executing exception-return instructions (e.g. MRET) will always mark any active LR/SC transaction as invalid.

Active Atomic Operation Indication

The "AMO_active" output net port is written by the model with a code indicating any current atomic memory operation while the instruction is active. The written codes are:
0: no atomic instruction active
1: AMOMIN active
2: AMOMAX active
3: AMOMINU active
4: AMOMAXU active
5: AMOADD active
6: AMOXOR active
7: AMOOR active
8: AMOAND active
9: AMOSWAP active
10: LR active
11: SC active

Interrupts

The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero.
The "nmi" port is an active-high NMI input. The processor resumes execution from the address specified using the "nmi_address" parameter when the NMI signal goes high. The "mcause" register is cleared to zero.
All other interrupt ports are active high. For each implemented privileged execution level, there are by default input ports for software interrupt, timer interrupt and external interrupt; for example, for Machine mode, these are called "MSWInterrupt", "MTimerInterrupt" and "MExternalInterrupt", respectively. When the N extension is implemented, ports are also present for User mode. Parameter "unimp_int_mask" allows the default behavior to be changed to exclude certain interrupt ports. The parameter value is a mask in the same format as the "mip" CSR; any interrupt corresponding to a non-zero bit in this mask will be removed from the processor and read as zero in "mip", "mie" and "mideleg" CSRs (and Supervisor and User mode equivalents if implemented).
Parameter "external_int_id" can be used to enable extra interrupt ID input ports on each hart. If the parameter is True then when an external interrupt is applied the value on the ID port is sampled and used to fill the Exception Code field in the "mcause" CSR (or the equivalent CSR for other execution levels). For Machine mode, the extra interrupt ID port is called "MExternalInterruptID".
The "deferint" port is an active-high artifact input that, when written to 1, prevents any pending-and-enabled interrupt being taken (normally, such an interrupt would be taken on the next instruction after it becomes pending-and-enabled). The purpose of this signal is to enable alignment with hardware models in step-and-compare usage.

Debug Mode

The model can be configured to implement Debug mode using parameter "debug_mode". This implements features described in Chapter 4 of the RISC-V External Debug Support specification (see References). Some aspects of this mode are not defined in the specification because they are implementation-specific; the model provides infrastructure to allow implementation of a Debug Module using a custom harness. Features added are described below.
Parameter "debug_mode" can be used to specify three different behaviors, as follows:
1. If set to value "vector", then operations that would cause entry to Debug mode result in the processor jumping to the address specified by the "debug_address" parameter. It will execute at this address, in Debug mode, until a "dret" instruction causes return to non-Debug mode. Any exception generated during this execution will cause a jump to the address specified by the "dexc_address" parameter.
2. If set to value "interrupt", then operations that would cause entry to Debug mode result in the processor simulation call (e.g. opProcessorSimulate) returning, with a stop reason of OP_SR_INTERRUPT. In this usage scenario, the Debug Module is implemented in the simulation harness.
3. If set to value "halt", then operations that would cause entry to Debug mode result in the processor halting. Depending on the simulation environment, this might cause a return from the simulation call with a stop reason of OP_SR_HALT, or debug mode might be implemented by another platform component which then restarts the debugged processor again.

Debug State Entry

The specification does not define how Debug mode is implemented. In this model, Debug mode is enabled by a Boolean pseudo-register, "DM". When "DM" is True, the processor is in Debug mode. When "DM" is False, mode is defined by "mstatus" in the usual way.
Entry to Debug mode can be performed in any of these ways:
1. By writing True to register "DM" (e.g. using opProcessorRegWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
2. By writing a 1 then 0 to net "haltreq" (using opNetWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
3. By writing a 1 to net "resethaltreq" (using opNetWrite) while the "reset" signal undergoes a negedge transition, followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
4. By executing an "ebreak" instruction when Debug mode entry for the current processor mode is enabled by dcsr.ebreakm, dcsr.ebreaks or dcsr.ebreaku.
In all cases, the processor will save required state in "dpc" and "dcsr" and then perform actions described above, depending in the value of the "debug_mode" parameter.

Debug State Exit

Exit from Debug mode can be performed in any of these ways:
1. By writing False to register "DM" (e.g. using opProcessorRegWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
2. By executing an "dret" instruction when Debug mode.
In both cases, the processor will perform the steps described in section 4.6 (Resume) of the Debug specification.

Debug Registers

When Debug mode is enabled, registers "dcsr", "dpc", "dscratch0" and "dscratch1" are implemented as described in the specification. These may be manipulated externally by a Debug Module using opProcessorRegRead or opProcessorRegWrite; for example, the Debug Module could write "dcsr" to enable "ebreak" instruction behavior as described above, or read and write "dpc" to emulate stepping over an "ebreak" instruction prior to resumption from Debug mode.

Debug Mode Execution

The specification allows execution of code fragments in Debug mode. A Debug Module implementation can cause execution in Debug mode by the following steps:
1. Write the address of a Program Buffer to the program counter using opProcessorPCSet;
2. If "debug_mode" is set to "halt", write 0 to pseudo-register "DMStall" (to leave halted state);
3. If entry to Debug mode was handled by exiting the simulation callback, call opProcessorSimulate or opRootModuleSimulate to resume simulation.
Debug mode will be re-entered in these cases:
1. By execution of an "ebreak" instruction; or:
2. By execution of an instruction that causes an exception.
In both cases, the processor will either jump to the debug exception address, or return control immediately to the harness, with stopReason of OP_SR_INTERRUPT, or perform a halt, depending on the value of the "debug_mode" parameter.

Debug Single Step

When in Debug mode, the processor or harness can cause a single instruction to be executed on return from that mode by setting dcsr.step. After one non-Debug-mode instruction has been executed, control will be returned to the harness. The processor will remain in single-step mode until dcsr.step is cleared.

Debug Ports

Port "DM" is an output signal that indicates whether the processor is in Debug mode
Port "haltreq" is a rising-edge-triggered signal that triggers entry to Debug mode (see above).
Port "resethaltreq" is a level-sensitive signal that triggers entry to Debug mode after reset (see above).

Debug Mask

It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
Value 0x002: enable debugging of PMP and virtual memory state;
Value 0x004: enable debugging of interrupt state.
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

Integration Support

This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

CSR Register External Implementation

If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.

LR/SC Active Address

Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active or if LR/SC locking is implemented externally as described above.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero.
Andes-specific cache, local memory and ECC behavior is not yet implemented, except for CSR state.
Andes Performance and Code Dense instructions and associated CSR state are implemented, but the EXEC.IT instruction supports in-memory table mode using the uitb CSR only (not hardwired mode).
PMP and PMA accesses that any-byte match but do not all-byte match are broken into separate smaller accesses that follow all-byte match rules.

Verification

All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
Also reference tests have been used from various sources including:
https://github.com/riscv/riscv-tests
https://github.com/ucb-bar/riscv-torture
The Imperas OVPsim RISC-V models are used in the RISC-V Foundations Compliance Framework as a functional Golden Reference:
https://github.com/riscv/riscv-compliance
where the simulated model is used to provide the reference signatures for compliance testing. The Imperas OVPsim RISC-V models are used as reference in both open source and commercial instruction stream test generators for hardware design verification, for example:
http://valtrix.in/sting/ from Valtrix
https://github.com/google/riscv-dv from Google
The Imperas OVPsim RISC-V models are also used by commercial and open source RISC-V Core RTL developers as a reference to ensure correct functionality of their IP.

References

The Model details are based upon the following specifications:
RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.2)
RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.10)
RISC-V Core-Local Interrupt Controller (CLIC) Version 0.9-draft-20191208
RISC-V External Debug Support Version 0.14.0-DRAFT
---- AndesCore_NX25_DS131_V1.0 DS131-10
---- AndeStar V5 Instruction Extension Specification (UMxxx-0.4, 2018-05-30)
---- AndeStar V5 Architecture and CSR Definitions (UM164-152, 2019-07-18)

Andes-Specific Extensions

Andes processors add various custom extensions to the basic RISC-V architecture. This model implements the following:
1: Hardware Stack Protection (if mmsc_cfg.HSP=1);
2: Physical Memory Attribute Unit (if mmsc_cfg.DPMA=1).
3: Performance Throttling (register interface only, if mmsc_cfg.PFT=1);
4: CSRs for CCTL Operations (register interface only, if mmsc_cfg.CCTLCSR=1);
5: Performance Extension instructions (if mmsc_cfg.EV5MPE=1);
6: CodeDense instructions (if mmsc_cfg.ECD=1);
7: Half-Precision Floating-Point instructions (if mmsc_cfg.EFHW=1).
Other Andes-specific extensions are not currently modeled. The exact set of supported extensions can be configured using parameter "andesExtensions/mmsc_cfg", which overrides the default value of the mmsc_cfg register (see detailed description below).

Andes-Specific Parameters

In addition to the base model RISC-V parameters, this model implements parameters allowing Andes-specific model features to be controlled. These parameters are documented below.

Parameter andesExtensions/mmsc_cfg

This parameter allows the value of the read-only mmsc_cfg register to be specified. Bits that affect behavior of the model are:
bit 3 (ECD): enables CodeDense instructions and uitb CSR.
bit 4 (PFT): determines presence of mpft_ctl register and affects implemented fields in mxstatus.
bit 5 (HSP): enables HW Stack protection, relevant CSRs and affects implemented fields in mxstatus.
bit 13 (EV5PE): enables Performance Extension support.
bit 15 (PMNDS): enables Andes-enhanced Performance Monitoring.
bit 16 (CCTLCSR): enables CCTL CSRs.
bit 30 (DPMA): enables the Physical Memory Attribute Unit and relevant CSRs.
Other bits can be set or cleared but do not affect model behavior.
Example: --override iss/cpu0/andesExtensions/mmsc_cfg=0x2028

Parameter andesExtensions/micm_cfg

This parameter allows the value of the read-only micm_cfg register to be specified. Bits that affect behavior of the model are:
bits 8:6 (ISZ): enables mcache_ctl CSR if non-zero.
bits 14:12 (ILMB): enables milmb CSR if non-zero.
Other bits can be set or cleared but do not affect model behavior, except that if any bit is non zero then IME/PIME bits in mxstatus are modeled.
Example: --override iss/cpu0/andesExtensions/micm_cfg=0

Parameter andesExtensions/mdcm_cfg

This parameter allows the value of the read-only mdcm_cfg register to be specified. Bits that affect behavior of the model are:
bits 8:6 (DSZ): enables mcache_ctl CSR if non-zero.
bits 14:12 (DLMB): enables mdlmb CSR if non-zero.
Other bits can be set or cleared but do not affect model behavior, except that if any bit is non zero then DME/DIME bits in mxstatus are modeled.
Example: --override iss/cpu0/andesExtensions/mdcm_cfg=0

Parameter andesExtensions/uitb

This parameter allows the value of the uitb register to be specified.
Example: --override iss/cpu0/andesExtensions/uitb=0

Parameter andesExtensions/milmb

This parameter allows the value of the milmb register to be specified.
Example: --override iss/cpu0/andesExtensions/milmb=0

Parameter andesExtensions/milmbMask

This parameter allows the mask of writable bits in the milmb register to be specified. The default value for this variant is 0xe (RWECC and ECCEN are writable, all other bits are read-only).
Example: --override iss/cpu0/andesExtensions/milmbMask=0xe

Parameter andesExtensions/mdlmb

This parameter allows the value of the mdlmb register to be specified.
Example: --override iss/cpu0/andesExtensions/mdlmb=0

Parameter andesExtensions/mdlmbMask

This parameter allows the mask of writable bits in the mdlmb register to be specified. The default value for this variant is 0xe (RWECC and ECCEN are writable, all other bits are read-only).
Example: --override iss/cpu0/andesExtensions/mdlmbMask=0xe

Parameter andesExtensions/PMA_grain

This parameter allows the grain size of Physical Memory Attribute regions to be specified. The default value for this variant is 0, meaning that PMA regions as small as 4 bytes are implemented.
Example: --override iss/cpu0/andesExtensions/PMA_grain=16

Hardware Stack Protection

Hardware Stack Protection is present on this variant (mmsc_cfg.HSP=1). Registers mhsp_ctl, msp_bound and msp_base are implemented.

Physical Memory Attribute Unit

The Physical Memory Attribute Unit is not present on this variant (mmsc_cfg.DPMA=0).

Performance Throttling

Performance Throttling registers are present on this variant (mmsc_cfg.PFT=1). Register mpft_ctl is present but has no behavior except for the effects on mxstatus, which are modeled.

Andes-Enhanced Performance Monitoring

Andes-Enhanced Performance Monitoring is present on this variant (mmsc_cfg.PMNDS=1).

CSRs for CCTL Operations

CSRs for CCTL Operation are not present on this variant (mmsc_cfg.CCTLCSR=0).

Andes-Specific Instructions

This section describes Andes-specific instructions implemented by this variant. Refer to Andes reference documentation for more information.

Performance Extension Instructions

ADDIGP
BBC
BBS
BEQC
BNEC
BFOS
BFOZ
LEA.h
LEA.w
LEA.d
LEA.b.ze
LEA.h.ze
LEA.w.ze
LEA.d.ze
LBGP
LBUGP
LHGP
LHUGP
LWGP
LWUGP
LDGP
SBGP
SHGP
SWGP
SDGP
FFB
FFZMISM
FFMISM
FLMISM

CodeDense Instructions

EXEC.IT
EX9.IT

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:

Table 2: Processor Instance 'cpu0' Parameters (Configurations)

ParameterValueDescription
endianlittleSelect processor endian (big or little)
simulateexceptionssimulateexceptionsCauses the processor simulate exceptions instead of halting
mips60The nominal MIPS for the processor

Table 3: Processor Instance 'cpu0' Parameters (Attributes)

Parameter NameValueType
variantNX25enum

Memory Map for processor 'cpu0' bus: 'bus0'

Processor instance 'cpu0' is connected to bus 'bus0' using master port 'INSTRUCTION'.

Processor instance 'cpu0' is connected to bus 'bus0' using master port 'DATA'.

Table 4: Memory Map ( 'cpu0' / 'bus0' [width: buswidth] )

Lo AddressHi AddressInstanceComponent
0x00x1FFFFFeilmram
remappableremappableAC97trap
remappableremappableAHBDECtrap
remappableremappableAPBBRGtrap
remappableremappableBMCtrap
remappableremappableDMACtrap
remappableremappableGPIOtrap
remappableremappableI2Ctrap
remappableremappableLCDCtrap
remappableremappableMACtrap
remappableremappablePITtrap
remappableremappablePLDMtrap
remappableremappablePLICtrap
remappableremappablePLIC_SWtrap
remappableremappableRTCtrap
remappableremappableSDCtrap
remappableremappableSMCtrap
remappableremappableSMUtrap
remappableremappableSPI1trap
remappableremappableSPI2trap
remappableremappableWDTtrap
0x2000000x2FFFFFedlmram
0x7FF00000x7FFFFFFstackram
0x800000000x801FFFFFspimemram
0xE60000000xE60000FFPLMTNCEPLMT100
0xF02000000xF020003FUART1ATCUART100
0xF03000000xF030003FUART2ATCUART100

Net Connections to processor: 'cpu0'

Table 5: Processor Net Connections ( 'cpu0' )

Net PortNetInstanceComponent
MTimerInterruptmtipPLMTNCEPLMT100



Peripheral Instances



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: BMC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 6: Configuration options (attributes) set for instance 'BMC'

AttributesValue
portAddress0xC0000000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: AHBDEC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 7: Configuration options (attributes) set for instance 'AHBDEC'

AttributesValue
portAddress0xE0000000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: MAC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 8: Configuration options (attributes) set for instance 'MAC'

AttributesValue
portAddress0xE0100000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: LCDC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 9: Configuration options (attributes) set for instance 'LCDC'

AttributesValue
portAddress0xE0200000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: SMC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 10: Configuration options (attributes) set for instance 'SMC'

AttributesValue
portAddress0xE0400000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: PLIC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 11: Configuration options (attributes) set for instance 'PLIC'

AttributesValue
portAddress0xE4000000
portSize0x1000
cbEnable1



Peripheral [andes.ovpworld.org/peripheral/NCEPLMT100/1.0] instance: PLMT

Limitations

Only used to demonstrate the execution of NX25 FreeRTOS
Register View and Basic Functionality

Description

NCEPLMT100 Platform-Level Machine Timer

Licensing

Open Source Apache 2.0

Reference

AndeStar_V5_Timer Specification UM167-11 2018-01-08

There are no configuration options set for this peripheral instance.



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: PLIC_SW

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 12: Configuration options (attributes) set for instance 'PLIC_SW'

AttributesValue
portAddress0xE6400000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: PLDM

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 13: Configuration options (attributes) set for instance 'PLDM'

AttributesValue
portAddress0xE6800000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: APBBRG

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 14: Configuration options (attributes) set for instance 'APBBRG'

AttributesValue
portAddress0xF0000000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: SMU

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 15: Configuration options (attributes) set for instance 'SMU'

AttributesValue
portAddress0xF0100000
portSize0x1000
cbEnable1



Peripheral [andes.ovpworld.org/peripheral/ATCUART100/1.0] instance: UART1

Limitations

Register View Model Only

Description

Andes UART

Licensing

Open Source Apache 2.0

Reference


Table 16: Configuration options (attributes) set for instance 'UART1'

AttributesValue
console1
finishOnDisconnect1



Peripheral [andes.ovpworld.org/peripheral/ATCUART100/1.0] instance: UART2

Limitations

Register View Model Only

Description

Andes UART

Licensing

Open Source Apache 2.0

Reference


Table 17: Configuration options (attributes) set for instance 'UART2'

AttributesValue
console1
finishOnDisconnect1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: PIT

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 18: Configuration options (attributes) set for instance 'PIT'

AttributesValue
portAddress0xF0400000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: WDT

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 19: Configuration options (attributes) set for instance 'WDT'

AttributesValue
portAddress0xF0500000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: RTC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 20: Configuration options (attributes) set for instance 'RTC'

AttributesValue
portAddress0xF0600000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: GPIO

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 21: Configuration options (attributes) set for instance 'GPIO'

AttributesValue
portAddress0xF0700000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: I2C

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 22: Configuration options (attributes) set for instance 'I2C'

AttributesValue
portAddress0xF0A00000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: SPI1

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 23: Configuration options (attributes) set for instance 'SPI1'

AttributesValue
portAddress0xF0B00000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: DMAC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 24: Configuration options (attributes) set for instance 'DMAC'

AttributesValue
portAddress0xF0C00000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: AC97

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 25: Configuration options (attributes) set for instance 'AC97'

AttributesValue
portAddress0xF0D00000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: SDC

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 26: Configuration options (attributes) set for instance 'SDC'

AttributesValue
portAddress0xF0E00000
portSize0x1000
cbEnable1



Peripheral [ovpworld.org/peripheral/trap/1.0] instance: SPI2

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Licensing

Open Source Apache 2.0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Table 27: Configuration options (attributes) set for instance 'SPI2'

AttributesValue
portAddress0xF0F00000
portSize0x1000
cbEnable1



AndesPlatforms
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