OVP Peripheral Model: AndesATCUART100
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Limitations
Register View Model Only
Description
Andes UART
Licensing
Open Source Apache 2.0
Location
The ATCUART100 peripheral model is located in an Imperas/OVP installation at the VLNV: andes.ovpworld.org / peripheral / ATCUART100 / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
finishOnDisconnect | bool | If set, disconnecting the port will cause the simulation to finish |
outfile | string | Name of file to write device output |
portFile | string | If portnum was specified as zero, write the port number to this file when it's known |
log | bool | If specified, serial output will go to simulator log |
console | bool | If specified, port number is ignored, and a console pops up automatically |
portnum | uns32 | If set, listen on this port. If set to zero, allocate a port from the pool and listen on that. |
infile | string | Name of file to use for device source |
charmode | bool | Description Set to true when the port is used to connect to a Telnet program and character mode is desired rather than the default Telnet line mode. When set to true a Telnet command sequence is sent at startup that configures the Telnet program into character mode. In addition null bytes are stripped from the data received. |
simulatebaud | bool | Description Set to true to simulate baud delay determined by the Divisor Latch register value and reference clock frequency. Set to false to run without delay - next read data is made available immediately upon read of Receiver Buffer Register. Defaults to false |
refClkFreq | uns32 | Frequency (in hertz) of reference clock rate used in baud rate calculation |
fifoSize | uns32 | Size of fifos |
uart16450 | bool | Run in 16450 mode (no FIFOs) |
connectnonblocking | bool | If set, simulation can begin before the connection is made |
xchars | uns32 | Width of console in characters |
ychars | uns32 | Height of console in characters |
record | string | Record external events into this file |
replay | string | Replay external events from this file |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
intOut | output | F (False) | Interrupt signal |
resetNet | input | F (False) | Reset signal |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x40 | T (True) | |
Table 3: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_MCR | 0x30 | 32 | Modem Control Register | | |
ab_LCR | 0x2c | 32 | Line Control Register | | |
ab_FCR | 0x28 | 32 | FIFO ControlRegister | | |
ab_IIR | 0x28 | 32 | Interrupt Identification Register | | |
ab_IER_DLM | 0x24 | 32 | Interrupt Enable Register / Divisor Latch MSB | | |
ab_THR_DLL | 0x20 | 32 | Transmitter Holding Register / Divisor Latch LSB | | |
ab_RBR_DLL | 0x20 | 32 | Receiver Buffer Register / Divisor Latch LSB | | |
ab_OSCR | 0x14 | 32 | Over Sample Control Register | | |
ab_CFG | 0x10 | 32 | Hardware Configure Register | | |
ab_IDREV | 0x0 | 32 | ID and Revision Register | | |
ab_LSR | 0x34 | 32 | Line Status Register | | |
ab_MSR | 0x38 | 32 | Modem Status Register | | |
ab_SCR | 0x3c | 32 | Scratch Register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'ATCUART100'