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Arc700

Model Information


This page provides detailed information about the OVP Fast Processor Model of the Synopsys ARC 700 core.
Processor IP owner is Synopsys ARC. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Synopsys ARC 700


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas Synopsys ARC 700 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The Synopsys ARC 700 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of Synopsys ARC 700 Fast Processor Model


Model Variant name: 700
Description:
    ARC 700 processor model (ARCv1 architecture)
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately.
    Instruction and data caches are not modeled, except for the auxiliary register interface.
    External host debug is not modeled, except for the auxiliary register interface.
    Real-world timing effects are not modeled. All instructions are assumed to complete in a single cycle.
Verification:
    Models have been validated correct in a cooperative project between Imperas and ARC
Reference:
    ARC Processor ARC6xx/ARC7xx Reference Documentation
Debugging:
    The model has been designed for debug using GNU gdb ARCompact/ARCv2 ISA elf32 version 7.5.1. To ensure correct behavior, enter the following command into gdb before attempting to connect to the processor:
     set architecture ARC700
    Failure to do this may cause the debugging session to fail because of g-packet size mismatch.
Features:
    The model implements the full ARCv1 instruction set.
    The exact set of core instructions present can be configured by a number of parameters: see information for opt-swap, opt-bitscan, opt-extended-arith and opt-multiply in the table below.
    Timer 0 and Timer 1 can be enabled using parameters opt-timer0 and opt-timer1, respectively.
    The versions of DCCM and ICCM build config registers can be specified using parameters opt-dccm-version and opt-iccm-version, respectively. The sizes of DCCM, ICCM0 and ICCM1 can be specified using parameters opt-dccm-size, opt-iccm0-size and opt-iccm1-size, respectively. Reset base addresses for the ICCMs can be specified using opt-iccm0-base and opt-iccm1-base. Note that the DCCM reset base address is architecturally defined (0x80000000) and not configurable. When CCMs are present, bus ports called DCCM0, ICCM0 and ICCM1 are created so that CCM contents may be viewed or modified externally by connecting to these ports. Parameter opt-internal-ccms specifies whether CCM memory is modeled internally or externally. If modeled externally, the CCMs must be implemented on a bus which is then connected to the CCM bus ports listed above (this parameter is ignored if CCM ports are unconnected; in that case, CCMs are always modeled internally). Parameter opt-reset-internal-ccms indicates that internally-modeled CCMs should be cleared to zero on a processor reset; if False, then internally-modeled CCMs retain their previous state after a reset.
    The set of core registers can be specified using parameter opt-extension-core-regs. This is a 64-bit value in which a 1-bit implies the presence of that core extension register. For example, a value of 0xf00000000ULL implies that extension registers r32-r35 should be configured.
    The reset value of the exception vector base register can be specified using parameter opt-intvbase-preset.
Auxiliary Register External Implementation:
    If parameter "enable-aux-bus" is True, an artifact 36-bit bus "Auxiliary" is enabled. Slave callbacks installed on this bus can be used to implement auxiliary register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). An auxiliary with 32-bit index 0xABCDEFGH is mapped on the bus at address 0xABCDEFGH0.

Model downloadable (needs registration and to be logged in) in package arc.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant 700 is available OVP_Model_Specific_Information_arc_700.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arc.ovpworld.org/processor/arc/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x5d
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
resetinput
watchdogoutput
irq5input
irq6input
irq7input
irq8input
irq9input
irq10input
irq11input
irq12input
irq13input
irq14input
irq15input
irq16input
irq17input
irq18input
irq19input
irq20input
irq21input
irq22input
irq23input
irq24input
irq25input
irq26input
irq27input
irq28input
irq29input
irq30input
irq31input

No FIFO Ports in 700.


Exceptions

NameCodeDescription
Reset0
ExternalMemoryBusError1
IllegalInstruction2
IllegalInstructionSequence3
DoubleFault4
OverlappingTLBEntries5
FatalTLBError6
FatalCacheError7
KernelDataMemoryError8
DFlushMemoryError9
IFetchMemoryError10
PrivilegeViolation19
DisabledExtension20
IFetchActionpointHit21
DataActionpointHit22
Trap24
ExtensionInstructionException25
MisalignedDataAccess28
Interrupt29

Execution Modes

ModeCodeDescription
Kernel0
User1

More Detailed Information

The 700 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arc_700.pdf.

Other Sites/Pages with similar information

Information on the 700 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



ArcProcessors
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