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OVP Virtual Platform: ArmVersatileExpress

This page provides detailed information about the OVP Virtual Platform Model of the arm.ovpworld.org ArmVersatileExpress platform.

Licensing

Open Source Apache 2.0

Description

This platform models the ARM Versatile Express development board with the Legacy memory map. It provides the peripherals required to boot and run Operating Systems such as Linux or Android. The main processor is an ARM Cortex-A9UP. This platform is deprecated in favor of the ArmVersatileExpress-CA9 platform which models additional behavior, including TrustZone.

Limitations

No known limitations for executing Linux operating system.

Reference

ARM Development Boards Versatile Express BaseBoard and ARM CoreTile Express

Location

The ArmVersatileExpress virtual platform is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / platform / ArmVersatileExpress / 1.0.

Platform Summary

Table : Components in platform

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

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Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments

Table 3: Platform Arguments

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Processor [arm.ovpworld.org/processor/arm/1.0] instance: cpu

Processor model type: 'arm' variant 'Cortex-A9MPx1' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arm.ovpworld.org/processor/arm/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arm_Cortex-A9MPx1.pdf

Description

ARM Processor Model

Licensing

Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
Source of model available under separate Imperas Software License Agreement.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
Performance Monitors are implemented as a register interface only except for the cycle counter, which is implemented assuming one instruction per cycle.
TLBs are architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.

Verification

Models have been extensively tested by Imperas. ARM Cortex-A models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.

Features

The precise set of implemented features in the model is defined by ID registers. Use overrides to modify these if required (for example override_PFR0 or override_AA64PFR0_EL1).

Core Features

Thumb-2 instructions are supported.
Trivial Jazelle extension is implemented.

Memory System

Security extensions are implemented (also known as TrustZone). Non-secure accesses can be made visible externally by connecting the processor to a 41-bit physical bus, in which case bits 39..0 give the true physical address and bit 40 is the NS bit.
VMSA secure and non-secure address translation is implemented.
TLB behavior is controlled by parameter ASIDCacheSize. If this parameter is 0, then an unlimited number of TLB entries will be maintained concurrently. If this parameter is non-zero, then only TLB entries for up to ASIDCacheSize different ASIDs will be maintained concurrently initially; as new ASIDs are used, TLB entries for less-recently used ASIDs are deleted, which improves model performance in some cases (especially when 16-bit ASIDs are in use). If the model detects that the TLB entry cache is too small (entry ejections are very frequent), it will increase the cache size automatically. In this variant, ASIDCacheSize is 8

Advanced SIMD and Floating-Point Features

SIMD and VFP instructions are implemented.
The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
Trapped exceptions not are implemented in this variant (FPTrap=0)

Generic Interrupt Controller

GIC block is implemented (GICv1, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters bus port. Secure register accesses are at offset 0x0 on this bus; for example, a secure access to GIC register ICDDCR can be observed by monitoring address 0x00001000. Non-secure accesses are at offset 0x80000000 on this bus; for example, a non-secure access to GIC register ICDDCR can be observed by monitoring address 0x80001000

Debug Mask

It is possible to enable model debug features in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled debug features are specified using a bitmask value, as follows:
Value 0x004: enable debugging of MMU/MPU mappings.
Value 0x020: enable debugging of reads and writes of GIC block registers.
Value 0x040: enable debugging of exception routing via the GIC model component.
Value 0x080: enable debugging of all system register accesses.
Value 0x100: enable debugging of all traps of system register accesses.
Value 0x200: enable verbose debugging of other miscellaneous behavior (for example, the reason why a particular instruction is undefined).
Value 0x400: enable debugging of Performance Monitor timers
Value 0x800: enable dynamic validation of TLB entries against in-memory page table contents (finds some classes of error where page table entries are updated without a subsequent flush of affected TLB entries).
All other bits in the debug bitmask are reserved and must not be set to non-zero values.

AArch32 Unpredictable Behavior

Many AArch32 instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.

Equal Target Registers

Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.

Floating Point Load/Store Multiple Lists

Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.

Floating Point VLD[2-4]/VST[2-4] Range Overflow

Instructions that load or store a fixed number of floating point registers (e.g. VST2, VLD2) are CONSTRAINED UNPREDICTABLE if the upper register bound exceeds the number of implemented floating point registers. In this model, these instructions load and store using modulo 32 indexing (consistent with AArch64 instructions with similar behavior).

If-Then (IT) Block Constraints

Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.

Use of R13

In architecture variants before ARMv8, use of R13 was described as CONSTRAINED UNPREDICTABLE in many circumstances. From ARMv8, most of these situations are no longer considered unpredictable. This model allows R13 to be used like any other GPR, consistent with the ARMv8 specification.

Use of R15

Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictableR15" as follows:
Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed (but are not interworking).
Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
In this variant, the default value of "unpredictableR15" is "undefined".

Unpredictable Instructions in Some Modes

Some instructions are described as CONSTRAINED UNPREDICTABLE in some modes only (for example, MSR accessing SPSR is CONSTRAINED UNPREDICTABLE in User and System modes). This model allows such use to be configured using the parameter "unpredictableModal", which can have values "undefined" or "nop". See the previous section for more information about the meaning of these values.
In this variant, the default value of "unpredictableModal" is "nop".

Integration Support

This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.

Memory Transaction Query

Two registers are intended for use within memory callback functions to provide additional information about the current memory access. Register transactPL indicates the processor execution level of the current access (0-3). Note that for load/store translate instructions (e.g. LDRT, STRT) the reported execution level will be 0, indicating an EL0 access. Register transactAT indicates the type of memory access: 0 for a normal read or write; and 1 for a physical access resulting from a page table walk.

Page Table Walk Query

A banked set of registers provides information about the most recently completed page table walk. There are up to six banks of registers: bank 0 is for stage 1 walks, bank 1 is for stage 2 walks, and banks 2-5 are for stage 2 walks initiated by stage 1 level 0-3 entry lookups, respectively. Banks 1-5 are present only for processors with virtualization extensions. The currently active bank can be set using register PTWBankSelect. Register PTWBankValid is a bitmask indicating which banks contain valid data: for example, the value 0xb indicates that banks 0, 1 and 3 contain valid data.
Within each bank, there are registers that record addresses and values read during that page table walk. Register PTWBase records the table base address, register PTWInput contains the input address that starts a walk, register PTWOutput contains the result address and register PTWPgSize contains the page size (PTWOutput and PTWPgSize are valid only if the page table walk completes). Registers PTWAddressL0-PTWAddressL3 record the addresses of level 0 to level 3 entries read, respectively. Register PTWAddressValid is a bitmask indicating which address registers contain valid data: bits 0-3 indicate PTWAddressL0-PTWAddressL3, respectively, bit 4 indicates PTWBase, bit 5 indicates PTWInput, bit 6 indicates both PTWOutput and PTWPgSize. For example, the value 0x73 indicates that PTWBase, PTWInput, PTWOutput, PTWPgSize and PTWAddressL0-L1 are valid but PTWAddressL2-L3 are not. Register PTWAddressNS is a bitmask indicating whether an address is in non-secure memory: bits 0-3 indicate PTWAddressL0-PTWAddressL3, respectively, bit 4 indicates PTWBase, bit 6 indicates PTWOutput (PTWInput is a VA and thus has no secure/non-secure info). Registers PTWValueL0-PTWValueL3 contain page table entry values read at level 0 to level 3. Register PTWValueValid is a bitmask indicating which value registers contain valid data: bits 0-3 indicate PTWValueL0-PTWValueL3, respectively.

Artifact Page Table Walks

Registers are also available to enable a simulation environment to initiate an artifact page table walk (for example, to determine the ultimate PA corresponding to a given VA). Register PTWI_EL1S initiates a secure EL1 table walk for a fetch. Register PTWD_EL1S initiates a secure EL1 table walk for a load or store (note that current ARM processors have unified TLBs, so these registers are synonymous). Registers PTW[ID]_EL1NS initiate walks for non-secure EL1 accesses. Registers PTW[ID]_EL2 initiate EL2 walks. Registers PTW[ID]_S2 initiate stage 2 walks. Registers PTW[ID]_EL3 initiate AArch64 EL3 walks. Finally, registers PTW[ID]_current initiate current-mode walks (useful in a memory callback context). Each walk fills the query registers described above.

MMU and Page Table Walk Events

Two events are available that allow a simulation environment to be notified on MMU and page table walk actions. Event mmuEnable triggers when any MMU is enabled or disabled. Event pageTableWalk triggers on completion of any page table walk (including artifact walks).

Artifact Address Translations

A simulation environment can trigger an artifact address translation operation by writing to the architectural address translation registers (e.g. ATS1CPR). The results of such translations are written to an integration support register artifactPAR, instead of the architectural PAR register. This means that such artifact writes will not perturb architectural state.

TLB Invalidation

A simulation environment can cause TLB state for one or more address translation regimes in the processor to be flushed by writing to the artifact register ResetTLBs. The argument is a bitmask value, in which non-zero bits select the TLBs to be flushed, as follows:
Bit 0: EL0/EL1 stage 1 secure TLB
Bit 1: EL0/EL1 stage 1 non-secure TLB

Halt Reason Introspection

An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.

System Register Access Monitor

If parameter "enableSystemMonitorBus" is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
bits 31:26 - zero
bit 25 - 1 if AArch64 access, 0 if AArch32 access
bit 24 - 1 if non-secure access, 0 if secure access
bits 23:20 - CRm value
bits 19:16 - CRn value
bits 15:12 - op2 value
bits 11:8 - op1 value
bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
bits 3:0 - zero
As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.

System Register Implementation

If parameter "enableSystemBus" is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 4: Processor Instance 'cpu' Parameters (Configurations)

Table 5: Processor Instance 'cpu' Parameters (Attributes)

Memory Map for processor 'cpu' bus: 'smbus'

Processor instance 'cpu' is connected to bus 'smbus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'smbus' using master port 'DATA'.

Table 6: Memory Map ( 'cpu' / 'smbus' [width: 32] )

Table 7: Bridged Memory Map ( 'cpu' / 'ddr2RemapBridge' / 'ddr2bus' [width: 32] )

Table 8: Bridged Memory Map ( 'cpu' / 'ddr2RamBridge' / 'ddr2bus' [width: 32] )

Net Connections to processor: 'cpu'

Table 9: Processor Net Connections ( 'cpu' )

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Peripheral Instances

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Peripheral [arm.ovpworld.org/peripheral/VexpressSysRegs/1.0] instance: sysRegs

Description

ARM Versatile Express System Registers

Limitations

Only select registers are modeled. See user.c for details.

Reference

ARM Motherboard Express ATX V2M-P1 Technical Reference Manual(ARM DUI 0447G), Section 4.3 Register Summary

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/SysCtrlSP810/1.0] instance: sysCtrl

Description

ARM SP810 System Control Registers

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM PrimeCell System Controller (SP810) Technical Reference Manual (ARM DDI 0254)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/AaciPL041/1.0] instance: aac1

Description

ARM PL041 PrimeCell Advanced Audio CODEC Interface Registers

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual (ARM DDI 0173)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/MmciPL181/1.0] instance: mmc1

Description

ARM PrimeCell Multimedia Card Interface (MMCI)

Limitations

None

Licensing

Open Source Apache 2.0

Reference

ARM PrimeCell Multimedia Card Interface (Pl180) Technical Reference Manual (ARM DDI 0172)

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/KbPL050/1.0] instance: kb1

Description

ARM PL050 PS2 Keyboard or mouse controller

Limitations

None

Reference

ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual (ARM DDI 0143)

Licensing

Open Source Apache 2.0

Table 10: Configuration options (attributes) set for instance 'kb1'

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Peripheral [arm.ovpworld.org/peripheral/KbPL050/1.0] instance: ms1

Description

ARM PL050 PS2 Keyboard or mouse controller

Limitations

None

Reference

ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual (ARM DDI 0143)

Licensing

Open Source Apache 2.0

Table 11: Configuration options (attributes) set for instance 'ms1'

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Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart0

Description

ARM PL011 UART

Limitations

This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference

ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing

Open Source Apache 2.0

Table 12: Configuration options (attributes) set for instance 'uart0'

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Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart1

Description

ARM PL011 UART

Limitations

This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference

ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing

Open Source Apache 2.0

Table 13: Configuration options (attributes) set for instance 'uart1'

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Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart2

Description

ARM PL011 UART

Limitations

This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference

ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing

Open Source Apache 2.0

Table 14: Configuration options (attributes) set for instance 'uart2'

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Peripheral [arm.ovpworld.org/peripheral/UartPL011/1.0] instance: uart3

Description

ARM PL011 UART

Limitations

This is not a complete model of the PL011. There is no modeling of physical aspects of the UART, such as baud rates etc.

Reference

ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183)

Licensing

Open Source Apache 2.0

Table 15: Configuration options (attributes) set for instance 'uart3'

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Peripheral [arm.ovpworld.org/peripheral/WdtSP805/1.0] instance: wdt1

Description

ARM SP805 Watchdog Registers.

Limitations

Does NOT model watchdog functionality, just provides registers to allow code to run.

Reference

ARM Watchdog Module (SP805) Technical Reference Manual (ARM DDI 0270)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/TimerSP804/1.0] instance: timer01

Description

Timer SP804 Module

Licensing

Open Source Apache 2.0

Limitations

none

Reference

ARM Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271)

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/TimerSP804/1.0] instance: timer23

Description

Timer SP804 Module

Licensing

Open Source Apache 2.0

Limitations

none

Reference

ARM Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271)

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/SerBusDviRegs/1.0] instance: dvi1

Description

Versatile Express Serial Bus DVI Registers

Licensing

Open Source Apache 2.0

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM Motherboard Express ATX V2M-P1 Technical Reference Manual(ARM DUI 0447G), Section 4.5.8 Two-wire serial bus interface, SBCon

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/RtcPL031/1.0] instance: rtc1

Description

ARM PL031 Real Time Clock (RTC)

Limitations

none

Reference

ARM PrimeCell Real Time Clock (PL031) Technical Reference Manual (ARM DDI 0224)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/CompactFlashRegs/1.0] instance: cf1

Description

ARM Versatile Express Compact Flash Interface Registers

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM Motherboard Express uATX (V2M-P1) Technical Reference Manual (ARM DDI 0447)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/LcdPL110/1.0] instance: lcd1

Description

ARM PL110 LCD Controller

Limitations

The VGA display refresh is not optimised resulting in the VGA peripheral causing a limit on the maximum performance of a platform it contains to be around 300 MIPS (actual dependent upon refresh rate of LCD).
The LCD peripheral utilises memory watchpoints to optimise display refresh. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.
Interrupts are not supported

Reference

ARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual (ARM DDI 0293)

Licensing

Open Source Apache 2.0

Table 16: Configuration options (attributes) set for instance 'lcd1'

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Peripheral [arm.ovpworld.org/peripheral/DMemCtrlPL341/1.0] instance: dmc1

Description

ARM PL341 Dynamic Memory Controller Registers

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM CoreLink DDR2 Dynamic Memory Controller (DMC-341) Technical Reference Manual (ARM DDI 0418)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/SMemCtrlPL354/1.0] instance: smc1

Description

PL354 Static Memory Controller

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual (ARM DDI 0380)

Licensing

Open Source Apache 2.0

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/TimerSP804/1.0] instance: timer45

Description

Timer SP804 Module

Licensing

Open Source Apache 2.0

Limitations

none

Reference

ARM Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271)

There are no configuration options set for this peripheral instance.

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Peripheral [ovpworld.org/peripheral/trap/1.0] instance: gpio0

Description

Open a port and allocate a region that is defined by parameters.
The region can be configured to act as standard memory or can report read/write accesses.

Licensing

Open Source Apache 2.0

Limitations

This peripheral cannot be used in a hardware description used to generate a TLM platform.

Reference

This is not based upon the operation of a real device but is intended to be used for bring up and development of new virtual platforms.

Table 17: Configuration options (attributes) set for instance 'gpio0'

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Peripheral [arm.ovpworld.org/peripheral/L2CachePL310/1.0] instance: l2regs

Description

ARM PL310 L2 Cache Control Registers

Licensing

Open Source Apache 2.0

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Reference

ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual (ARM DDI 0246)

There are no configuration options set for this peripheral instance.

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Peripheral [smsc.ovpworld.org/peripheral/LAN9118/1.0] instance: eth0

Description

Fully functional Model of SMSC LAN9118 for Arm Versatile Express platforms. For full details please consult README-EMAC.txt

Licensing

Open Source Apache 2.0

Limitations

See README-EMAC.txt

Reference

SMSC LAN9118 High Performance single-chip 10/100 Non-PCI Ethernet Controller Datasheet Revision 1.5 (07-11-08)

There are no configuration options set for this peripheral instance.

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Peripheral [philips.ovpworld.org/peripheral/ISP1761/1.0] instance: usb0

Description

Functional Model of USB Philips ISP1761 for Arm Versatile Express platforms. For full details please consult README-OTG.txt

Licensing

Open Source Apache 2.0

Limitations

- Only host mode is supported. - DMA modes are not supported for the moment, only the mandatory slave mode is implemented. - Control and bulk transfer types are currently implemented. No interrupt and isochronous transfers yet. - Tested only the attachment of a single host device. The HSOTG controller's root hub has a single port, so only one device can be attached to it. This device could be a hub, though. Currently we support only one non-hub device. - Hot plug events are currently unsupported.

Reference

Philips/NXP

There are no configuration options set for this peripheral instance.

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Peripheral [arm.ovpworld.org/peripheral/SmartLoaderArmLinux/1.0] instance: smartLoader

Licensing

Open Source Apache 2.0

Description

Psuedo-peripheral to perform memory initialisation for an ARM based Linux kernel boot: Loads Linux kernel image file and (optional) initial ram disk image into memory. Writes ATAG data into memory. Writes tiny boot code at physical memory base that configures the registers as expected by Linux Kernel and then jumps to boot address (image load address by default).

Limitations

Only supports little endian

Reference

See ARM Linux boot requirements in Linux source tree at documentation/arm/Booting

Table 18: Configuration options (attributes) set for instance 'smartLoader'