Model Information

This page provides detailed information about the OVP Fast Processor Model of the ARM Cortex-R82MPx6 core.
Processor IP owner is ARM Holdings. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap

Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools

This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for ARM Cortex-R82MPx6

An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas ARM Cortex-R82MPx6 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The ARM Cortex-R82MPx6 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of ARM Cortex-R82MPx6 Fast Processor Model

Model Variant name: Cortex-R82MPx6
Description:
    ARM Processor Model
Licensing:
    Usage of binary model under license governing simulator usage.
    
    Note that for models of ARM CPUs the license includes the following terms:
    
    Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
    
    If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
    
    In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
    
    Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
    
    The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
    
    The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
    
    Source of model available under separate Imperas Software License Agreement.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. ISB, CP15ISB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. The model does not implement speculative fetch behavior. The branch cache is not modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous (as if the memory was of Strongly Ordered or Device-nGnRnE type). Data barrier instructions (e.g. DSB, CP15DSB) are treated as NOPs, with the exception of any undefined instruction behavior, which is modeled. Cache manipulation instructions are implemented as NOPs, with the exception of any undefined instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    Performance Monitors are implemented as a register interface only except for the cycle counter, which is implemented assuming one instruction per cycle.
    Self-hosted Trace Extension registers are implemented as a register interface only.
    Debug registers are implemented but non-functional (which is sufficient to allow operating systems such as Linux to boot). Debug state is not implemented.
    The GICv3 block is implemented without any ITS. Implementation-defined GICR registers for control of LPIs (GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR and GICR_SYNCR) are all implemented.
    The optional ITCM region is not implemented.
    The optional DTCM region is not implemented.
    The optional LLP region is not implemented.
    The optional LLRAM region is not implemented.
    The optional SPP region is not implemented.
Verification:
    Models have been extensively tested by Imperas. ARM Cortex models have been successfully used by customers to simulate SMP Linux, Ubuntu Desktop, VxWorks and ThreadX on Xilinx Zynq virtual platforms.
Features:
    The precise set of implemented features in the model is defined by ID registers. Use overrides to modify these if required (for example override_PFR0 or override_AA64PFR0_EL1).
Core Features:
    AArch64 is implemented at EL2, EL1 and EL0.
    The following ARMv8.0 core features are implemented: FEAT_CSV2_1p1, FEAT_CSV3, FEAT_DGH, FEAT_SB, FEAT_SPECRES, FEAT_SSBS, FEAT_SSBS2.
    The following ARMv8.1 core features are implemented: FEAT_LSE, FEAT_PAN, FEAT_RDM.
    The following ARMv8.2 core features are implemented: FEAT_DotProd, FEAT_DPB, FEAT_DPB2, FEAT_FHM, FEAT_FP16, FEAT_IESB, FEAT_PAN2, FEAT_RAS (with no error records), FEAT_UAO, FEAT_XNX.
    The following ARMv8.3 core features are implemented: FEAT_LRCPC, FEAT_FCMA, FEAT_FPAC, FEAT_JSCVT, FEAT_PAuth, FEAT_PAuth2.
    The following ARMv8.4 core features are implemented: FEAT_DIT, FEAT_FlagM, FEAT_IDST, FEAT_LRCPC2, FEAT_LSE2, FEAT_RASv1p1, FEAT_S2FWB, FEAT_SEL2, FEAT_TLBIOS, FEAT_TLBIRANGE.
Memory System:
    Security extensions are implemented (also known as TrustZone). To make non-secure accesses visible externally, override ID_AA64MMFR0_EL1.PARange to specify the required physical bus size (32, 36, 40, 42, 44, 48 or 52 bits) and connect the processor to a bus one bit wider (33, 37, 41, 43, 45, 49 or 53 bits, respectively). The extra most-significant bit is the NS bit, indicating a non-secure access. If non-secure accesses are not required to be made visible externally, connect the processor to a bus of exactly the size implied by ID_AA64MMFR0_EL1.PARange.
    LPA (large physical address extension) is implemented as standard in ARMv8.
Advanced SIMD and Floating-Point Features:
    SIMD and VFP instructions are implemented.
    The model implements trapped exceptions if FPTrap is set to 1 in MVFR0 (for AArch32) or MVFR0_EL1 (for AArch64). When floating point exception traps are taken, cumulative exception flags are not updated (in other words, cumulative flag state is always the same as prior to instruction execution, even for SIMD instructions). When multiple enabled exceptions are raised by a single floating point operation, the exception reported is the one in least-significant bit position in FPSCR (for AArch32) or FPCR (for AArch64). When multiple enabled exceptions are raised by different SIMD element computations, the exception reported is selected from the lowest-index-number SIMD operation. Contact Imperas if requirements for exception reporting differ from these.
    Trapped exceptions not are implemented in this variant (FPTrap=0)
Generic Timer:
    Generic Timer is present. Use parameter "override_timerScaleFactor" to specify the counter rate as a fraction of the processor MIPS rate (e.g. 10 implies Generic Timer counters increment once every 10 processor instructions).
Generic Interrupt Controller:
    GIC block is implemented (GICv3, including security extensions). Accesses to GIC registers can be viewed externally by connecting to the 32-bit GICRegisters and GICDRegisters bus ports. Secure register accesses are at offset 0x0 on these busses; for example, a secure access to GICD register GICD_CTLR can be observed by monitoring address 0x00000000 of bus GICDRegisters. Non-secure accesses are at offset 0x80000000 on these busses; for example, a non-secure access to GICD register GICD_CTLR can be observed by monitoring address 0x80000000 of bus GICDRegisters
    GIC Distributor registers are located at address 0x2f000000. Use parameter "override_GICv3_DistributorBase" to change this if required.
    The internal GIC block can be disabled by raising signal GICCDISABLE, in which case the GIC needs to be modeled using a platform component instead. Input signals vfiq_CPU and virq_CPU can be used by this component to raise virtual FIQ and IRQ interrupts on cores in the cluster if required.
Debug Mask:
    It is possible to enable model debug features in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled debug features are specified using a bitmask value, as follows:
    Value 0x004: enable debugging of MMU/MPU mappings.
    Value 0x020: enable debugging of reads and writes of GIC block registers.
    Value 0x040: enable debugging of exception routing via the GIC model component.
    Value 0x080: enable debugging of all system register accesses.
    Value 0x100: enable debugging of all traps of system register accesses.
    Value 0x200: enable verbose debugging of other miscellaneous behavior (for example, the reason why a particular instruction is undefined).
    Value 0x400: enable debugging of Performance Monitor timers
    All other bits in the debug bitmask are reserved and must not be set to non-zero values.
Integration Support:
    This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
Halt Reason Introspection:
    An artifact register HaltReason can be read to determine the reason or reasons that a processor is halted. This register is a bitfield, with the following encoding: bit 0 indicates the processor has executed a wait-for-event (WFE) instruction; bit 1 indicates the processor has executed a wait-for-interrupt (WFI) instruction; and bit 2 indicates the processor is held in reset.
System Register Access Monitor:
    If parameter "enableSystemMonitorBus" is True, an artifact 32-bit bus "SystemMonitor" is enabled for each PE. Every system register read or write by that PE is then visible as a read or write on this artifact bus, and can therefore be monitored using callbacks installed in the client environment (use opBusReadMonitorAdd/opBusWriteMonitorAdd or icmAddBusReadCallback/icmAddBusWriteCallback, depending on the client API). The format of the address on the bus is as follows:
    bits 31:26 - zero
    bit 25 - 1 if AArch64 access, 0 if AArch32 access
    bit 24 - 1 if non-secure access, 0 if secure access
    bits 23:20 - CRm value
    bits 19:16 - CRn value
    bits 15:12 - op2 value
    bits 11:8 - op1 value
    bits 7:4 - op0 value (AArch64) or coprocessor number (AArch32)
    bits 3:0 - zero
    As an example, to view non-secure writes to writes to CNTFRQ_EL0 in AArch64 state, install a write monitor on address range 0x020e0330:0x020e0333.
System Register Implementation:
    If parameter "enableSystemBus" is True, an artifact 32-bit bus "System" is enabled for each PE. Slave callbacks installed on this bus can be used to implement modified system register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). The format of the address on the bus is the same as for the system monitor bus, described above.

Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant Cortex-R82MPx6 is available OVP_Model_Specific_Information_arm_Cortex-R82MPx6.pdf.

Configuration

Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xb7
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port Type	Name	Width (bits)	Description
master	INSTRUCTION	32
master	DATA	32
master	GICRegisters	32
master	GICDRegisters	32

SystemC Signal Ports (Net Ports)

Port Type	Name	Description
SPI32	input
SPI33	input
SPI34	input
SPI35	input
SPI36	input
SPI37	input
SPI38	input
SPI39	input
SPI40	input
SPI41	input
SPI42	input
SPI43	input
SPI44	input
SPI45	input
SPI46	input
SPI47	input
SPI48	input
SPI49	input
SPI50	input
SPI51	input
SPI52	input
SPI53	input
SPI54	input
SPI55	input
SPI56	input
SPI57	input
SPI58	input
SPI59	input
SPI60	input
SPI61	input
SPI62	input
SPI63	input
SPI64	input
SPI65	input
SPI66	input
SPI67	input
SPI68	input
SPI69	input
SPI70	input
SPI71	input
SPI72	input
SPI73	input
SPI74	input
SPI75	input
SPI76	input
SPI77	input
SPI78	input
SPI79	input
SPI80	input
SPI81	input
SPI82	input
SPI83	input
SPI84	input
SPI85	input
SPI86	input
SPI87	input
SPI88	input
SPI89	input
SPI90	input
SPI91	input
SPI92	input
SPI93	input
SPI94	input
SPI95	input
SPIVector	input
periphReset	input
GICCDISABLE	input
PPI16_CPU0_0	input
PPI17_CPU0_0	input
PPI18_CPU0_0	input
PPI19_CPU0_0	input
PPI20_CPU0_0	input
PPI21_CPU0_0	input
PPI22_CPU0_0	input
PPI23_CPU0_0	input
PPI24_CPU0_0	input
PPI25_CPU0_0	input
PPI26_CPU0_0	input
PPI27_CPU0_0	input
PPI28_CPU0_0	input
PPI29_CPU0_0	input
PPI30_CPU0_0	input
PPI31_CPU0_0	input
CNTVIRQ_CPU0_0	output
CNTPNSIRQ_CPU0_0	output
CNTHPSIRQ_CPU0_0	output
IRQOUT_CPU0_0	output
FIQOUT_CPU0_0	output
CLUSTERIDAFF1	input
CLUSTERIDAFF2	input
CLUSTERIDAFF3	input
RVBARADDRx_CPU0_0	input
CFGEND_CPU0_0	input
reset_CPU0_0	input
fiq_CPU0_0	input
irq_CPU0_0	input
sei_CPU0_0	input
vfiq_CPU0_0	input
virq_CPU0_0	input
vsei_CPU0_0	input
AXI_SLVERR_CPU0_0	input
CP15SDISABLE_CPU0_0	input
PMUIRQ_CPU0_0	output
PPI16_CPU1_0	input
PPI17_CPU1_0	input
PPI18_CPU1_0	input
PPI19_CPU1_0	input
PPI20_CPU1_0	input
PPI21_CPU1_0	input
PPI22_CPU1_0	input
PPI23_CPU1_0	input
PPI24_CPU1_0	input
PPI25_CPU1_0	input
PPI26_CPU1_0	input
PPI27_CPU1_0	input
PPI28_CPU1_0	input
PPI29_CPU1_0	input
PPI30_CPU1_0	input
PPI31_CPU1_0	input
CNTVIRQ_CPU1_0	output
CNTPNSIRQ_CPU1_0	output
CNTHPSIRQ_CPU1_0	output
IRQOUT_CPU1_0	output
FIQOUT_CPU1_0	output
RVBARADDRx_CPU1_0	input
CFGEND_CPU1_0	input
reset_CPU1_0	input
fiq_CPU1_0	input
irq_CPU1_0	input
sei_CPU1_0	input
vfiq_CPU1_0	input
virq_CPU1_0	input
vsei_CPU1_0	input
AXI_SLVERR_CPU1_0	input
CP15SDISABLE_CPU1_0	input
PMUIRQ_CPU1_0	output
PPI16_CPU2_0	input
PPI17_CPU2_0	input
PPI18_CPU2_0	input
PPI19_CPU2_0	input
PPI20_CPU2_0	input
PPI21_CPU2_0	input
PPI22_CPU2_0	input
PPI23_CPU2_0	input
PPI24_CPU2_0	input
PPI25_CPU2_0	input
PPI26_CPU2_0	input
PPI27_CPU2_0	input
PPI28_CPU2_0	input
PPI29_CPU2_0	input
PPI30_CPU2_0	input
PPI31_CPU2_0	input
CNTVIRQ_CPU2_0	output
CNTPNSIRQ_CPU2_0	output
CNTHPSIRQ_CPU2_0	output
IRQOUT_CPU2_0	output
FIQOUT_CPU2_0	output
RVBARADDRx_CPU2_0	input
CFGEND_CPU2_0	input
reset_CPU2_0	input
fiq_CPU2_0	input
irq_CPU2_0	input
sei_CPU2_0	input
vfiq_CPU2_0	input
virq_CPU2_0	input
vsei_CPU2_0	input
AXI_SLVERR_CPU2_0	input
CP15SDISABLE_CPU2_0	input
PMUIRQ_CPU2_0	output
PPI16_CPU3_0	input
PPI17_CPU3_0	input
PPI18_CPU3_0	input
PPI19_CPU3_0	input
PPI20_CPU3_0	input
PPI21_CPU3_0	input
PPI22_CPU3_0	input
PPI23_CPU3_0	input
PPI24_CPU3_0	input
PPI25_CPU3_0	input
PPI26_CPU3_0	input
PPI27_CPU3_0	input
PPI28_CPU3_0	input
PPI29_CPU3_0	input
PPI30_CPU3_0	input
PPI31_CPU3_0	input
CNTVIRQ_CPU3_0	output
CNTPNSIRQ_CPU3_0	output
CNTHPSIRQ_CPU3_0	output
IRQOUT_CPU3_0	output
FIQOUT_CPU3_0	output
RVBARADDRx_CPU3_0	input
CFGEND_CPU3_0	input
reset_CPU3_0	input
fiq_CPU3_0	input
irq_CPU3_0	input
sei_CPU3_0	input
vfiq_CPU3_0	input
virq_CPU3_0	input
vsei_CPU3_0	input
AXI_SLVERR_CPU3_0	input
CP15SDISABLE_CPU3_0	input
PMUIRQ_CPU3_0	output
PPI16_CPU4_0	input
PPI17_CPU4_0	input
PPI18_CPU4_0	input
PPI19_CPU4_0	input
PPI20_CPU4_0	input
PPI21_CPU4_0	input
PPI22_CPU4_0	input
PPI23_CPU4_0	input
PPI24_CPU4_0	input
PPI25_CPU4_0	input
PPI26_CPU4_0	input
PPI27_CPU4_0	input
PPI28_CPU4_0	input
PPI29_CPU4_0	input
PPI30_CPU4_0	input
PPI31_CPU4_0	input
CNTVIRQ_CPU4_0	output
CNTPNSIRQ_CPU4_0	output
CNTHPSIRQ_CPU4_0	output
IRQOUT_CPU4_0	output
FIQOUT_CPU4_0	output
RVBARADDRx_CPU4_0	input
CFGEND_CPU4_0	input
reset_CPU4_0	input
fiq_CPU4_0	input
irq_CPU4_0	input
sei_CPU4_0	input
vfiq_CPU4_0	input
virq_CPU4_0	input
vsei_CPU4_0	input
AXI_SLVERR_CPU4_0	input
CP15SDISABLE_CPU4_0	input
PMUIRQ_CPU4_0	output
PPI16_CPU5_0	input
PPI17_CPU5_0	input
PPI18_CPU5_0	input
PPI19_CPU5_0	input
PPI20_CPU5_0	input
PPI21_CPU5_0	input
PPI22_CPU5_0	input
PPI23_CPU5_0	input
PPI24_CPU5_0	input
PPI25_CPU5_0	input
PPI26_CPU5_0	input
PPI27_CPU5_0	input
PPI28_CPU5_0	input
PPI29_CPU5_0	input
PPI30_CPU5_0	input
PPI31_CPU5_0	input
CNTVIRQ_CPU5_0	output
CNTPNSIRQ_CPU5_0	output
CNTHPSIRQ_CPU5_0	output
IRQOUT_CPU5_0	output
FIQOUT_CPU5_0	output
RVBARADDRx_CPU5_0	input
CFGEND_CPU5_0	input
reset_CPU5_0	input
fiq_CPU5_0	input
irq_CPU5_0	input
sei_CPU5_0	input
vfiq_CPU5_0	input
virq_CPU5_0	input
vsei_CPU5_0	input
AXI_SLVERR_CPU5_0	input
CP15SDISABLE_CPU5_0	input
PMUIRQ_CPU5_0	output

No FIFO Ports in Cortex-R82MPx6.

Exceptions

Name	Code	Description
Reset	0
Undefined	1
SupervisorCall	2
HypervisorCall	4
PrefetchAbort	5
DataAbort	6
HypervisorTrap	7
IRQ	8
FIQ	9
IllegalState	10
MisalignedPC	11
MisalignedSP	12
SError	13

Execution Modes

Mode	Code	Description
EL0t	0
EL1t	4
EL1h	5
EL2t	8
EL2h	9

More Detailed Information

The Cortex-R82MPx6 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_Cortex-R82MPx6.pdf.

Other Sites/Pages with similar information

Information on the Cortex-R82MPx6 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.