OVP Peripheral Model: ArmLcdPL110

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


ARM PL110 LCD Controller


The VGA display refresh is not optimised resulting in the VGA peripheral causing a limit on the maximum performance of a platform it contains to be around 300 MIPS (actual dependent upon refresh rate of LCD).

The LCD peripheral utilises memory watchpoints to optimise display refresh. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.

Interrupts are not supported


ARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual (ARM DDI 0293)


Open Source Apache 2.0


The LcdPL110 peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / LcdPL110 / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

busOffsetuns32Set an offset for the display memory window
scanDelayuns32Set the rate of the display refresh (default 20000)
noGraphicsboolDisable the graphics output
resolutionstringSet the resolution of the display. VGA (default), SVGA, XVGA/XGA.
pixelChecksumboolWrite a checksum of each screen contents
packedPixelsboolOnly valid when 24BPP used. Set to enable pixel packing in data buffer. Default 24 bit pixel stored in 32-bit data word.
titlestringSet the title of the display window

Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
irqoutputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: memory

Table 2: Bus Slave Port: memory

NameSize (bytes)Must Be ConnectedDescription
memory0x1F (False)

No address blocks have been defined for this slave port.

Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 4: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_timing00x032LCD Timing 0
ab_timing10x432LCD Timing 1
ab_timing20x832LCD Timing 2
ab_timing30xc32LCD Timing 3
ab_upbase0x1032LCD UP Base
ab_lpbase0x1432LCD LP Base
ab_imsc0x1832LCD IMSC
ab_control0x1c32LCD Control
ab_int_status0x2032LCD RIS
ab_int_mis0x2432LCD MIS
ab_int_clr0x2832LCD ICR
ab_upbase20x2c32LCD UP current
ab_lpbase20x3032LCD LP current

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'LcdPL110'

Platform NameVendor

Page was generated in 0.0233 seconds