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OVP Peripheral Model: ArmLcdPL110

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Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

ARM PL110 LCD Controller

Limitations

The VGA display refresh is not optimised resulting in the VGA peripheral causing a limit on the maximum performance of a platform it contains to be around 300 MIPS (actual dependent upon refresh rate of LCD).

The LCD peripheral utilises memory watchpoints to optimise display refresh. This requires the use of ICM memory for the frame buffers, which currently may stop its use in SystemC TLM2 platforms.

Interrupts are not supported

Reference

ARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual (ARM DDI 0293)

Licensing

Open Source Apache 2.0

Location

The LcdPL110 peripheral model is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / peripheral / LcdPL110 / 1.0.

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Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

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Net Ports

This model has the following net ports:

Table 1: Net Ports

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Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: memory

Table 2: Bus Slave Port: memory

No address blocks have been defined for this slave port.

Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1

Table 4: Bus Slave Port: bport1 Registers:

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Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'LcdPL110'